Sacrificial Oxide Layer Research Articles

Hybrid Molecular Beam Epitaxy for Single-Crystalline Oxide Membranes with Binary Oxide Sacrificial Layers.

The advancement in thin-film exfoliation for synthesizing oxide membranes has led to possibilities for creating artificially assembled heterostructures with structurally and chemically incompatible materials. The sacrificial layer method is a promising approach to exfoliate as-grown films from a compatible material system, allowing for their integration with dissimilar materials. Nonetheless, the conventional sacrificial layers often possess an intricate stoichiometry, thereby constraining their practicality and adaptability, particularly when considering techniques such as molecular beam epitaxy (MBE). This is where easy-to-grow binary alkaline-earth-metal oxides with a rock salt crystal structure are useful. These oxides, which include (Mg, Ca, Sr, Ba)O, can be used as a sacrificial layer covering a much broader range of lattice parameters compared to conventional sacrificial layers and are easily dissolvable in deionized water. In this study, we show the epitaxial growth of the single-crystalline perovskite SrTiO3 (STO) on sacrificial layers consisting of crystalline SrO, BaO, and Ba1-xCaxO films, employing a hybrid MBE method. Our results highlight the rapid (≤5 min) dissolution of the sacrificial layer when immersed in deionized water, facilitating the fabrication of millimeter-sized STO membranes. Using high-resolution X-ray diffraction, atomic-force microscopy, scanning transmission electron microscopy, impedance spectroscopy, and scattering-type near-field optical microscopy (SNOM), we demonstrate single-crystalline STO membranes with bulk-like intrinsic dielectric properties. The employment of alkaline earth metal oxides as sacrificial layers is likely to simplify membrane synthesis, particularly with MBE, thus expanding the research and application possibilities.

Porphyrin-Based MOF Thin Film on Transparent Conducting Oxide: Investigation of Growth, Porosity and Photoelectrochemical Properties.

Synthesizing metal-organic frameworks (MOFs) composites with a controlled morphology is an important requirement to access materials of desired patterning and composition. Since the last decade, MOF growth from sacrificial metal oxide layer is increasingly developed as it represents an efficient pathway to functionalize a large number of substrates. In this study, porphyrin-based Al-PMOF thin films were grown on conductive transparent oxide substrates from sacrificial layers of ALD-deposited alumina oxide. The control of the solvent composition and the number of atomic layer deposition (ALD) cycles allow us to tune the crystallinity, morphology and thickness of the produced thin films. Photophysical studies evidence that Al-PMOF thin films present light absorption and emission properties governed by the porphyrinic linker, without any quenching upon increasing the film thickness. Al-PMOF thin films obtained through this methodology present a remarkably high optical quality both in terms of transparency and coverage. The porosity of the samples is demonstrated by ellipsometry and used for Zn(II) insertion inside the MOF thin film. The multifunctional transparent, porous and luminescent thin film grown on fluorine-doped tin oxide (FTO) is used as an electrode capable of photoinduced charge separation upon simulated sunlight irradiation.

High Frequency MEMS Capacitive Mirror for Space Applications.

Free space optics laser communication using modulating retroreflectors (MR) is a challenging application for an active mirror, due to the high frequencies (>100 kHz) required to enable sufficient data transfer. Micro Electromechanical (MEMS) mirrors are a promising option for high-frequency applications, given the very small moving mass typical of such devices. Capacitive MEMS mirrors are presented here for free space communications, based on a novel fabrication sequence that introduces a single-layer thin film aluminum mirror structure with an underlying silicon oxide sacrificial layer. The use of aluminum instead of gold as a mirror layer diminishes the heating generated by the absorption of the sun's radiation once the mirrors exit the earth's atmosphere. Thanks to the novel fabrication sequence, the presented mirror devices have a full range actuation voltage of less than 40 V, and a high operational frequency with an eigenfrequency above 2 MHz. The devices were manufactured and characterized, and their main parameters were obtained from experimental data combined with finite element analysis, thus enabling future design optimization of the reported MEMS technology. By optical characterization of the far field diffraction pattern, good mirror performance was demonstrated.

Plasmonic Gold Trimers and Dimers with Air-Filled Nanogaps.

The subwavelength confinement of light energy in the nanogaps formed between adjacent plasmonic nanostructures provides the foundational basis for nanophotonic applications. Within this realm, air-filled nanogaps are of central importance because they present a cavity where application-specific nanoscale objects can reside. When forming such configurations on substrate surfaces, there is an inherent difficulty in that the most technologically relevant nanogap widths require closely spaced nanostructures separated by distances that are inaccessible through standard electron-beam lithography techniques. Herein, we demonstrate an assembly route for the fabrication of aligned plasmonic gold trimers with air-filled vertical nanogaps having widths that are defined with spatial controls that exceed those of lithographic processes. The devised procedure uses a sacrificial oxide layer to define the nanogap, a glancing angle deposition to impose a directionality on trimer formation, and a sacrificial antimony layer whose sublimation regulates the gold assembly process. By further implementing a benchtop nanoimprint lithography process and a glancing angle ion milling procedure as additional controls over the assembly, it is possible to deterministically position trimers in periodic arrays and extend the assembly process to dimer formation. The optical response of the structures, which is characterized using polarization-dependent spectroscopy, surface-enhanced Raman scattering, and refractive index sensitivity measurements, shows properties that are consistent with simulation. This work, hence, forwards the wafer-based processing techniques needed to form air-filled nanogaps and place plasmonic energy at site-specific locations.

Conformal atomic layer etching for Ge based on sacrificial oxide with higher Gibbs free energy of formation

Layer-by-layer conformal atomic layer etching (cALE) for Ge is demonstrated by alternating processes consisting of the self-limiting deposition of a sacrificial oxide and the self-stop etching of the sacrificial oxide and interfacial layer (IL). The critical point of cALE is the formation of the GeOx IL between Ge and the sacrificial oxide. Accordingly, a sacrificial oxide with higher Gibbs free energy of formation was selected and investigated in the cALE process for the formation of more GeOx to increase the Ge etching rate. The cALE process presents a linear dependence of the etching depth on the cALE cycles, along with an accurate etching rate (several Å per cALE cycle) and a low surface roughness of Ge. In addition, the transmission electron microscopy images of three-dimensional fin structures of Ge demonstrate the damage-free Ge surface as well as the conformal etching of cALE. The result shows that the cALE technique can achieve precise etching of Ge accompanied with the self-limiting, self-stop, damage-free, layer-by-layer, and conformal characteristics, which is highly favorable to Ge-based nanoelectronic devices in advanced semiconductor technology nodes.

High yield preparation of flexible single-crystalline 4H-silicon carbide nanomembranes via buried micro-trenches

We present the fabrication of flexible single-crystalline 4H-silicon carbide (SiC) nanomembranes (NMs) with a centimeter size. The 4H–SiC NMs has been released from a 4H–SiC-on-insulator (4H–SiCOI) wafer and transferred to a flexible adhesive tape. By introducing buried micron trenches (BMTs) in the sacrificial buried oxide (BOX) layer in 4H–SiCOI, the lateral etching rate is increased by about three times, crucial to the fabrication of large-size 4H–SiC NMs with a high yield. The prepared 4H–SiC NMs show single-crystalline quality, ultra-smooth surface, and excellent ultraviolet (UV) absorption performance, paving the way toward the development of 4H–SiC based flexible and stretchable optoelectronic devices. The proposed BMTs assisted release method also provides a universal and effective way to obtain large scale and intact single-crystalline NMs for flexible applications. We present the fabrication of flexible single-crystalline 4H-silicon carbide nanomembranes (NMs) with a high yield. The introduced buried micron trenches (BMTs) in the sacrificial layer in 4H–SiCOI facilities the release of NMs. The prepared 4H–SiC NMs show single-crystalline quality, ultra-smooth surface, and excellent ultraviolet (UV) absorption performance. • Flexible, intact and single-crystalline 4H–SiC nanomembranes (NMs) were prepared with high yield. • The SiC NMs show excellent ultraviolet absorption performance. • The demonstrated method provides an effective way to obtain single-crystalline NMs for flexible applications.

Manufacturing and Testing of Radio Frequency MEMS Switches Using the Complementary Metal Oxide Semiconductor Process.

A radio frequency microelectromechanical system switch (MSS) manufactured by the complementary metal oxide semiconductor (CMOS) process is presented. The MSS is a capacitive shunt type. Structure for the MSS consists of coplanar waveguide (CPW) lines, a membrane, and springs. The membrane locates over the CPW lines. The surface of signal line for the CPW has a silicon dioxide dielectric layer. The fabrication of the MSS contains a CMOS process and a post-process. The MSS has a sacrificial oxide layer after the CMOS process. In the post-processing, a wet etching of buffer oxide etch (BOE) etchant is employed to etch the sacrificial oxide layer, so that the membrane is released. Actuation voltage for the MSS is simulated using the CoventorWare software. The springs have a low stiffness, so that the actuation voltage reduces. The measured results reveal that actuation voltage for the MSS is 10 V. Insertion loss for the MSS is 0.9 dB at 41 GHz and isolation for the MSS is 30 dB at 41 GHz.

Wet-chemical etching of FIB lift-out TEM lamellae for damage-free analysis of 3-D nanostructures

Reducing ion beam damage from the focused ion beam (FIB) during fabrication of cross sections is a well-known challenge for materials characterization, especially cross sectional characterization of nanostructures. To address this, a new method has been developed for cross section fabrication enabling high resolution transmission electron microscopy (TEM) analysis of 3-D nanostructures free of surrounding material and free of damage detectable by TEM analysis. Before FIB processing, nanopillars are encapsulated in a sacrificial oxide which acts as a protective layer during FIB milling. The cross sectional TEM lamella containing the nanopillars is then mounted and thinned with some modifications to conventional FIB sample preparation that provide stability for the lamella during the following wet-chemical dip etch. The wet-chemical etch of the TEM lamella removes the sacrificial oxide layer, freeing the nanopillars from any material that would obscure TEM imaging. Both high resolution TEM and aberration corrected scanning TEM images of Si/SiGe pillars with diameters down to 30 nm demonstrate the successful application of this approach.

Investigation on the oxide-oxide galvanic displacement reactions employed in the preparation of electrocatalytic layers

Galvanic displacement reactions between sacrificial oxide layers and metal cations, leading to the formation of secondary oxide layers, have been studied with the aim of collecting new experimental evidence on their mechanism. The study has been carried out by combining electrochemical methods, SEM-EDS and XPS depth profiling. Both porous and compact PbO2 layers have been used as sacrificial oxides and reacted, in different experiments, with: (i) a single low-valent cation, (ii) two cations in sequential exchange reactions or (iii) two cations simultaneously. The experimental results converged to show (i) a lack of correlation between the reaction driving force and the secondary oxide growth rate, (ii) the incorporation of cations from solution at the secondary oxide/electrolyte interface, (iii) the transport of Pb species through the growing secondary oxide layer and (iv) a major effect of mass transport on the growth rate.

Corrosion Potential Modulation on Lead Anodes Using Water Oxidation Catalyst Coatings

The oxidation of water to form oxygen gas provides charge balance for the cathodic deposition of metals, such as zinc, in the electrorefining industry. This is a corrosive, four-electron electrochemical reaction that causes deterioration of lead-silver alloy anodes employed in these processes. A sacrificial manganese oxide layer on the anode surface, formed in-situ from manganese sulfate, is used in industry to reduce the corrosion rate of these anodes by preferentially enabling water oxidation rather than lead dissolution. Still, it is poorly understood how the activity of manganese oxide as a water oxidation catalyst relates to its anticorrosive properties. Here, we show how the presence of water oxidation catalysts both formed in-situ (including the industry standard manganese oxide) and heterogenized prior to electrolysis on lead anodes affect the corrosion potential of these anodes. We find that corrosion potential under dynamic polarization conditions is the parameter most affected by the coatings formed in-situ and applied ex-situ prior to electrolysis.

Nanomeshes at Liquid Interfaces: From Free‐Standing Hole Arrays toward Metal–Insulator–Metal Architectures

AbstractThe superior optical properties of metamaterials often rely on hierarchical structures in the sub‐wavelength regime comprising stacks of individually patterned layers. For the fabrication of metamaterials in the visible regime, specific top‐down lithographic methods have been developed. These techniques, however, have several inherent drawbacks such the lack of scalability and low production speeds. Here, a simple and modular approach for the construction of multilayer metal–insulator–metal structures based on the transfer of metal nanohole arrays via liquid interfaces is demonstrated. Gold nanohole arrays are used as model systems that are prepared via nanosphere lithography on a zinc oxide sacrificial layer. Exploiting an interface mediated method, the prepared nanohole arrays are subsequently transferred onto arbitrary hydrophilic or hydrophobic substrates without compromising the high quality of the nanomeshes. Two approaches to stack such nanostructured layers with nanometer precision in a rapid way are demonstrated. Finally, the high mechanical stability of only 100 nm thick gold nanohole arrays allows for the preparation of free‐standing nanomeshes in the order of several hundreds of square‐micrometers.

Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved. Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced. Figure 1

Transfer Printed Flexible and Stretchable Thin Film Solar Cells Using a Water‐Soluble Sacrificial Layer

Recently, the rapid and significant progress in the development of various stretchable electronics has triggered intense research interest. Although the remarkable features of transfer printing processes have enabled the use of inorganic crystalline semiconductors in various types of stretchable devices, including solar cells, light‐emitting diodes, circuits, and photodetectors, there are few examples of stretchable electronics using thin film semiconductors. Transfer printing of inorganic amorphous thin film semiconductors remains a challenge because no suitable sacrificial layer is available. To meet this challenge, a water‐soluble germanium oxide sacrificial layer is developed. Stretchable inorganic amorphous thin film solar cells are produced using a transfer printing process with a water‐soluble sacrificial layer. This first attempt to fabricate stretchable solar cells with inorganic amorphous thin film semiconductors significantly broadens the scope of solar cell applications. Moreover, the germanium oxide sacrificial layer can be used in other thin film electronics applications.

An advanced tunnel oxide layer process for 65 nm NOR floating-gate flash memories

An advanced tunnel oxide layer process for 65 nm NOR-type floating-gate flash memory is proposed to improve tunnel oxide quality by an additive sacrificial oxide layer growth. The sacrificial oxide layer process effectively controls the thickness variation of tunnel oxide and improves the flatness of the SiO2/Si interface across the active area. The interface traps’ generation during program/erase cycling of flash cells is found to be reduced, and the reliability property is significantly improved as compared to flash cells without the sacrificial oxide layer process. The technology is applicable to further scaled floating-gate flash memories.

Nanogaps Fabricated from Electrodeposited Fe-Ni-Co Nanowires

Nanogap electrodes are elements of nanoscale microfluidic devices and sensors, and have been prepared by different techniques, as recently reviewed by Li et al.1 Their use in biomedical microelectromechanical systems (Bio-MEMS) for molecular detection requires the gap dimensions to be of the same order as the target molecule ~10 nm. Several effective strategies to fabricate nanogap electrodes include: on-wire lithography with segmented nanowires that are etched, 2 -3 using a mechanically controllable break junction,4 focused ion beam lithography,5 and by electrodepositing a metal directly onto separated lithographic wires to fill in the separated space to reduce the gap size to the nanometer range.6 The approach studied here is to create electrodeposited nanowires with a sacrificial layer to create the gap. Examples of chemically etched inner regions of electrodeposited nanowires have been demonstrated in trilayers of Au-Ni-Au,2,7 Au-Ag-Au,2-3 Au-Cu-Au,8 and the quinary FeNiCo-Au-Cu-Au-FeNiCo.8 In this work, tri-layered nanowires with FeNiCo and either Cu or oxide regions, FeNiCo-Cu-FeNiCo, and FeNiCo-oxide-FeNiCo, are electrodeposited using the template method. Nanogaps are prepared by chemically etching the sacrifice layer, i.e., Cu, or the oxide layer, prepared in different ways. Conditions to ensure that the wires are robust before etching and that they form reproducible nanogaps are presented. Experimental Conditions used to deposit and etch the nanowires were determined from rotating cylinder studies. Fe-rich, FeNiCo conditions were selected. The electrodeposition of the tri-layered nanowires was fabricated in a standard three electrode cell with a polycarbonate membrane as a template. FeNiCo was pulsed deposited from a sulfamate-boric acid electrolyte at a pH of 2 and at a temperature of 40 °C. Cu was either galvanostatically deposited or deposited by displacement from a citrate-boric acid electrolyte at a pH of 2 and at room temperature. All nanowires were removed from the template and placed on a substrate to chemically etch the sacrificial, middle layer in an etching solution containing: 0.01 M sodium sulfate, 0.45 M sodium citrate, and 0.40 M boric acid at a pH of 5. The nanowires and their resulting gaps were inspected by FE-SEM (Hitachi S4800). Results and Discussion Figures 1 and 2 show gap regions between two FeNiCo segments that are generated after the etching step. Figure 1 shows examples of gaps created from a sacrificial Cu layer, and Figure 2 shows gaps generated from a sacrificial oxide layer. The Cu region was created by either electrodeposition, Figure 1 (a), or by displacement, Figure 1 (b). The smallest gaps were achieved using the Cu displacement technique. The gaps were not reflective of the charge passed during Cu deposition and was attributed to the generation of an Fe-rich oxide. Replacing the Cu sacrificial layer completely with an Fe-rich oxide layer, Figure 2, also resulted in reproducible gaps < 10 nm. Figure 2 (a) shows the gap region when the applied potential, after the first FeNiCo layer, was maintained at the open circuit potential (OCP), and Figure 2 (b) shows the gap created at an anodic potential value of 0.4 V vs OCP. When the potential was anodic, the second FeNiCo layer created a “tip” at the gap surface. Conclusion Sub-10 nm nanogaps were developed through template electrodeposition via etching of a Cu or oxide layer. The results suggest that a sacrificial Cu layer is effective, but unnecessary, and that a nano-gap can be created by the generation of an oxide from the FeNiCo layer at OCP. The oxide can also impart a tip shaping effect when it is created at an applied potential that is in the anodic region. Acknowledgement The authors thank Roche Diagnostics for generous support of this project. References T. Li, W. Hu and Z. Zhu, Adv. Mater. 22, 286 (2010).L. Qin, S. Park, L. Huang, and C. A. Mirkin, Science 309, 113 (2005).S. H. Liu, J. B. H. Tok, Z. N. Bao, Nano Lett. 5, 1071 (2005).M. A. Reed, C. Zhou, C.J. Muller, T. P. Burgin, J. Tour, Science, 278, 252 (1997).T. Nagase, T. Kubota, S. Mashiko, Thin Solid Films 438, 374 (2003).Y. Kashimura, H. Nakashima, K. Furukawa, K.Torimitsu, Thin Sold Films 438, 317 (2003).B. Widt, P. Mali, and P. C. Searson, Langmuir, 22, 10528 (2006).H. Kim, S. A. Soper, E. J. Podlaha, ECS Trans. 53, 9 (2013). Figure 1

A Capacitive Ammonia Sensor Using the Commercial 0.18 μm CMOS Process

The project presents an ammonia sensor with heater on-a-chip manufactured using the commercial 0.18 μm CMOS (complementary metal oxide semiconductor) process. The ammonia sensor is composed of a sensitive film, interdigital electrodes and a polysilicon heater. The sensor is a capacitive type and the sensitive film is ZrO2that is prepared by sol-gel method. The sensor requires a post-process to remove the sacrificial oxide layer and coat the ZrO2film on the interdigital electrodes. When the sensitive film absorbs ammonia vapor, the capacitance of the sensor generates a change. Experimental results show that the sensitivity of the ammonia sensor is 2.47 pF/ppm at 270 °C.

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90 %RH.

Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization

Highly biaxially oriented linearly arranged poly-Si thin films were formed by double line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and energetically stable Σ3 grains boundary were observed dominantly. Silicon grains were elongated in the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were fabricated. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low temperature (≦550 o C) by a metal gate self-aligned process.The TFTs were fabricated as follows. A-Si of 150 nm thickness and cap SiO2 of 100 nm thickness were deposited on a quartz substrate. CW laser crystallization with double-line spot irradiation (wavelength: 532 nm, laser power: 8.5 W, scan speed: 0.25 cm/s) on a-Si was carried out, and lateral-crystallized poly-Si was formed. After the laser crystallization, the cap SiO2 was etched using buffered HF aqueous solution (BHF), and lithography and dry etching (Cl2: 40 sccm, HBr: 40 sccm) were performed in order to pattern the poly-Si active layer. Next, gate SiO2 of 50 nm thickness was deposited by inductively coupled plasma chemical vapor deposition (ICP CVD, SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and a Mo gate electrode of 200 nm thickness was deposited by sputtering method. After lithography patterning, wet etching of Mo was carried out with a solution of H3PO4: HNO3: CH3COOH: H2O= 400: 25: 50: 25 and the gate electrode was formed. A self–aligned source and drain system was formed by As ion doping (ion dose: 2×1015 cm-2, acceleration voltage: 66 keV) using the Mo gate electrode as the mask. Activation annealing treatment was carried out at 550o C in N2 ambient for 30 min. A sacrificial oxide layer in the S/D region was removed using BHF. After the removal, 150-nm-thick interlayer insulation films were deposited by atmospheric pressure chemical vapor deposition (APCVD), and the contact hole was etched using BHF. A Mo metal pad was deposited by sputtering method, and finally sintering processing was carried out at 400 o C in H2ambient for 30 min. Figure 1 shows a microphotograph of the fabricated DLB-CLC poly-Si TFT.A TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. At the electron field effect mobility, its variation was within 10% at same crystallization region. High-performance TFTs with DLB-CLC were demonstrated, however it was found that off-leakage current was relatively large. The leakage current mechanism was investigated by measuring temperature dependence of the TFT characteristics. The field-effect mobilities at the ON region were proportional to T-1.5 as shown in Fig. 2. The result shows the phonon scattering was dominant as same as single silicon crystal. On the other hand, in the OFF region, the electrical conductivity shows logarithmic behavior as a function of exp{-EB/kBT} as shown in Fig. 3. This leakage current shows that there are many trap states in the grain boundaries.

An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

Characterization of in-depth cavity distribution after thermal annealing of helium-implanted silicon and gallium nitride

Single-crystalline silicon wafers covered with sacrificial oxide layer and epitaxially grown gallium nitride layers were implanted with high-fluence helium ions (2–6×1016cm−2) at energies of 20–30keV. Thermal annealings at 650–1000°C, 1h were performed on the Si samples and rapid thermal annealings at 600–1000°C, 120s under N2 were performed on the GaN samples. The as-implanted samples and the near-surface cavity distributions of the annealed samples were investigated with variable angle spectroscopic ellipsometry. In-depth defect profiles and cavity profiles can be best described with multiple independent effective medium sublayers of varying ratio of single-crystal/void. The number of sublayers was chosen to maximize the fit quality without a high parameter cross-correlation. The dependence of the implantation fluence, oxide layer thickness and annealing temperature on the cavity distribution was separately investigated. The ellipsometric fitted distributions were compared and cross-checked with analyses of transmission electron micrographs where the average surface cavity was determined sublayer by sublayer. The in-depth profiles were also compared with simulations of He and vacancy distributions.