Oxide n-MOSFETs Research Articles

Intermittency-induced criticality in the random telegraph noise of nanoscale UTBB FD-SOI MOSFETs

The drain current in nanoscale fully depleted ultra-thin body and buried oxide n-MOSFETs is studied in terms of critical dynamics. The time series formed by the measured current through the channel of the MOSFET, appears to have the form of random telegraph noise (RTN). This timeseries is analyzed by the Method of Critical Fluctuation (MCF). Its dynamics are compatible with critical intermittency. According to the quantitative analysis performed, the current-value distributions are compatible with the spontaneous symmetry breaking phenomenon; in addition, it also carries information of criticality according to the corresponding power law. Finally, MCF analysis identified traces of tri-critical dynamics.

Physical mechanism of performance adjustment in selective buried oxide n-MOSFETs

Physical mechanism of performance adjustment in selective buried oxide n-MOSFETs

Optimisation of fully depleted SiGe channel with raised source/drain buried oxide nMOSFET

A fully depleted silicon-germanium (SiGe) n-channel heterojunction MOSFET with raised buried oxide in the source/drain is reported under the consideration that channel is made of SiGe and source/drain regions is made of silicon (Si). Due to the raised buried oxide source/drain region, it provides better current due to the improvement of mobility in the channel region and also reduce the surface scattering effects. Bandgap engineering has been done to improve the electrical behaviour of the device. Simulation work for different parameters on the device has been carried out and presented in the paper. The electrical characteristics of the proposed device are optimised by varying the device dimensions. Effect of mole fraction on threshold voltage (VTH), Subthreshold swing (SS), ION and IOFF current ratio is analysed. It is observed that due to presence of SiGe channel and the raised source/drain, the proposed device shows enhancement in electrical characteristics. A CMOS inverter through proposed device has been implemented and the effect of mole fraction on its characteristic is reported. Average delay increases as mole fraction increases.

Optimisation of fully depleted SiGe channel with raised source/drain buried oxide nMOSFET

A fully depleted silicon-germanium (SiGe) n-channel heterojunction MOSFET with raised buried oxide in the source/drain is reported under the consideration that channel is made of SiGe and source/drain regions is made of silicon (Si). Due to the raised buried oxide source/drain region, it provides better current due to the improvement of mobility in the channel region and also reduce the surface scattering effects. Bandgap engineering has been done to improve the electrical behaviour of the device. Simulation work for different parameters on the device has been carried out and presented in the paper. The electrical characteristics of the proposed device are optimised by varying the device dimensions. Effect of mole fraction on threshold voltage (VTH), Subthreshold swing (SS), ION and IOFF current ratio is analysed. It is observed that due to presence of SiGe channel and the raised source/drain, the proposed device shows enhancement in electrical characteristics. A CMOS inverter through proposed device has been implemented and the effect of mole fraction on its characteristic is reported. Average delay increases as mole fraction increases.

Chaotic Behavior of Random Telegraph Noise in Nanoscale UTBB FD-SOI MOSFETs

Low frequency noise in nanoscale fully depleted ultra-thin body and buried oxide n-MOSFETs is not as random (stochastic) as it appears to be. The fluctuation of the drain current in such nano-devices, under certain bias conditions, exhibits complex random telegraph noise (RTN) that is usually observed in chaotic systems. Indeed, the deterministic chaotic nature of this noise-like variation is confirmed by means of the combined calculation of established nonlinear dynamics metrics. Specifically, the correlation dimension, the phase portrait of the reconstructed chaotic attractor, and the Lyapunov spectrum, conclude for a hyperchaotic behavior of the complex RTN with fractal characteristics.

Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin box SOI MOSFETs suitable for circuit simulators

A detailed study of the hot-carrier degradation in nano-scale fully depleted ultra-thin body and buried oxide n-MOSFETs is presented. The degradation mechanisms were identified based on static current–voltage measurements. The degradation of the transistor was explained by considering generation of traps at the gate dielectric/Si interface and traps located within a tunneling distance of the interface. All stress parameters are considered describing with semi-empirical relations their impact on the transistor parameters. Based on our analytical compact model, we propose an aging hot-carrier model predicting with good accuracy the device degradation stressed under different bias conditions using a unique set of model parameters.

Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

The hot carrier (HC)-induced traps in nanoscale fully depleted ultrathin body and buried oxide nMOSFETs are investigated by low-frequency noise (LFN) measurements in the frequency and time domains. The measured noise spectra are composed of 1/f and Lorentzian-type components. The Lorentzian noise is due to either generation–recombination noise or random telegraph noise (RTN). Based on the LFN results, the effect of the HC stress on fully depleted silicon-on-insulator MOSFETs is investigated after short- and long-time stress. The capture and emission time constants responsible for the RTN noise were calculated as the average duration time of the high/low drain current state, respectively. Analysis of RTN traps detected in fresh and HC-stressed devices indicates that the RTN amplitude is uncorrelated to the trap time constants, i.e., the impact of the trap depth from the interface is masked by that of the trap location over the channel. The overall results lead to an analytical expression for the RTN amplitude, enabling to predict the RTN changes from the subthreshold to the above-threshold region.

Influence of gate voltage on gate-induced drain leakage current in ultra-thin gate oxide and ultra-short channel LDD nMOSFET's

The influence of gate voltage VG on gate induced drain leakage (GIDL) current is studied in LDD nMOSFET with a gate oxide of 1.4nm and a channel length of 100nm. It is found that the split phenomena of ln(Id/(VDG-1.2))-1/(VDG-1.2) curves under different VG values occurs, which are different from the large MOSFET. Through comparing varieties of ln(Id/(VDG-1.2)) of different VG values, the mechanism of this split phenomenon is obtained. This is ascribed to the change of the hole-tunneling part of GIDL current under different VG values. The absolute value of ln(Id/(VDG-1.2)) curve slope decrease with |VG| value decreasing . It is further found that the values of slope c and intercept d of ln(Id/(VDG-1.2)) curves are linear with VG and the slopes of c and d are 3.09 and -0.77, respectively. The values of c and d quantificationally show the influence of VG on the GIDL current in an ultra-thin ultra-short MOSFET. On the basis of these results, a new GIDL current model including VG is proposed.

The impact of gate–image charge on RTS amplitudes in ultra-thin gate oxide n-MOSFETs

An experimental study of RTS (random telegraph signal) noise amplitudes in ultra-thin gate oxide n-MOSFETs biased in sub-threshold and linear regions was conducted. At the same time, a modified model integrating effects of trapped charge and its gate image charge on the carrier number and mobility fluctuations in the conducting channel was presented. Compared with the widely used model, the newly built model fits the experimental RTS noise data of ultra-thin gate oxide n-MOSFETs better than the former one. By employing this model in the extraction of dynamic border trap characteristics by RTS noise means in ultra-thin gate oxide n-MOSFETs, a more accurate result can be expected.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs

On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate- to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.

Low voltage substrate current: a monitor for interface states generation in ultra-thin oxide n-MOSFETs under constant voltage stresses

The low voltage substrate current (Ib) has been studied based on generation kinetics and used as a monitor of interface states (Nit) generation for ultra-thin oxide n-MOSFETs under constant voltage stress. It is found that the low voltage Ib is formed by electrons tunnelling through interface states, and the variations of Ib(ΔIb) are proportional to variations of Nit (ΔNit). The Nit energy distributions were determined by differentiating Nit(Vg). The results have been compared with that measured by using gate diode technique.

Performance and reliability of ultra-thin oxide nMOSFETs under variable body bias

This experimental study investigates the performance and the reliability of nMOSFETs with channel length down to 90 nm and an equivalent oxide thickness of about 1.5 nm under variable body bias. Forward body bias allows to achieve a significant improvement in terms of drive capability especially for low voltage applications, while reverse body bias can be used to reduce the standby power. It is shown that forward body bias improves the lifetime associated with channel hot carrier stress, while it does not alter the time dependent dielectric breakdown process. This work indicates that the combined use of forward and reverse body bias is a powerful approach for extending the scalability of CMOS devices.

Performance and Reliability of Strained-Silicon nMOSFETs With SiN Cap Layer

A complete comparison of performance and reliability between polysilicon gate/SiON oxide nMOSFETs with and without SiN cap layer is presented. The uniaxial tensile strain induced by the cap layer causes an improvement in the channel current drive capability without degrading the noise performance. The gain in the transconductance, for the strained devices, was found to decrease for increasing channel lengths and for higher channel fields. Similar robustness against hot carrier stress, bias-temperature instability, and time to breakdown were found between strained and unstrained-silicon devices, confirming the advantages of strain technology

N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis

This paper presents oxide trap characterization of nitrided and non-nitrided gate oxide N-MOSFETs using low frequency noise (LFN) measurements. The identification of defects generated by the gate oxide growth and the nitridation process is carried out using random telegraph signal noise analysis. Significant properties of traps induced by the nitridation process are pointed out. Main trap parameters, such as their nature, capture and emission times, cross-sections, energy levels, and position with respect to the Si/SiO 2 interface, are extracted. These results illustrate the potential of noise investigation for oxide characterizations.

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -incorporated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> laminated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> multimetal stack oxide n-MOSFET such as lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , higher drive current, and an improved channel electron mobility are reported. Dy <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sample also shows a better immunity for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> instability and less severe charge trapping characteristics. Two different rationed Dy <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility

The breakdown characteristics of ultra-thin gate oxide n-MOSFET under voltage stress

The characteristics of the TDDB (Time-dependent dielectric breakdown) under the CVS (constant voltage stress) and the gate current model of devices under V-ramp stress were studied in the 1.4nm-thick n-MOSFET. The degradation and failure mechanisms were analyzed. The gate current is produced by the tunneling, the electron surmounting and percolation. During the stress process, the created traps in the oxide not only debase the height of the SiO2 barrier, but also diminish the breadth of the barrier. Every trap engenders a conduction path. These paths enhance the gate current, degrade the device performance and prolong the broken-time of the gate oxide.

Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.

Conduction mechanism of ultra-thin gate oxide n-MOSFET after soft breakdown

The conduction mechanism of ultra-thin gate oxide n-metal-oxide-semiconductor fi eld effect transistor (n-MOSFET) after soft breakdown is studied in this paper. It is found that in a certain range of gate voltage Vg, the gate cur r ent Ig follows the Fowler-Nordheim-like tunneling mechanism, and the experimen tal tunneling barrier b is 0936 eV in average, which is much smal ler t han the interface barrier of Si/SiO2 We think that after soft brea kdown, the electrons existing in the quantization energy levels of the Si/SiO2 interface , not directly tunnel to the oxide conduction band, but tunnel to the oxide defe ct band. b is determined by both the defect band energy level and t he qu antization energy level of the tunneling electrons. With rising experimental tem perature, the tunneling of high energy level electron is also increasing, which reduces b gradually.

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V D=1.8 V. We present a comprehensive study on the I– V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET ( V thn) of between 0.70 and 0.72 V and a saturation current ( I DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V thn of between 0.85 and 0.90 V and an I DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.