Abstract
The characteristics of the TDDB (Time-dependent dielectric breakdown) under the CVS (constant voltage stress) and the gate current model of devices under V-ramp stress were studied in the 1.4nm-thick n-MOSFET. The degradation and failure mechanisms were analyzed. The gate current is produced by the tunneling, the electron surmounting and percolation. During the stress process, the created traps in the oxide not only debase the height of the SiO2 barrier, but also diminish the breadth of the barrier. Every trap engenders a conduction path. These paths enhance the gate current, degrade the device performance and prolong the broken-time of the gate oxide.
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