Oxide Electric Field Research Articles

Gate leakage mechanisms in strained Si devices

This work investigates gate leakage mechanisms in advanced strained Si∕SiGe metal-oxide-semiconductor field-effect transistor (MOSFET) devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure, and device processing on gate oxide leakage characteristics are analyzed in detail. In state of the art MOSFETs, gate oxides are only a few nanometers thick. In order to minimize power consumption, leakage currents through the gate must be controlled. However, modifications to the energy band structure, Ge diffusion due to high temperature processing, and Si∕SiGe material quality may all affect gate oxide leakage in strained Si devices. We show that at high oxide electric fields where gate leakage is dominated by Fowler-Nordheim tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. This is a direct result of strain-induced splitting of the conduction band states. However, for device operating regimes at lower oxide electric fields Poole-Frenkel emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Gate oxide interface trap density exhibits a dissimilar behavior and is highly sensitive to Ge atoms at the oxidizing surface, degrading with increasing thermal budget. Consequently advanced strained Si∕SiGe devices are inadvertently subject to a potential tradeoff between power consumption (gate leakage current) and device reliability (gate oxide interface quality).

NBTI Study on PMOS Devices with TiN/HfO2 Gate Stack and Process Induced Strain

We investigate the effect of process induced strain on Negative Bias Temperature Instability (NBTI) for devices with TiN/HfO2 gate stacks. Devices with compressive Contact Etch Stop Layer (CESL), SiGe Source/Drain, and devices with a combination of both SiGe and CESL were studied and compared to reference devices. We decouple the effect of processing conditions in order to assure correct interpretation of the results. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with process induced strain. In addition, we performed an Arrhenius study showing that Si-H bonds under strain exhibit similar activation energies as Si-H bonds without strain, indicating that no favorable conditions for interface states generation are created by the strain.

Analysis of Gate Leakage in Strained Si MOSFETs

This work investigates gate leakage mechanisms in advanced strained Si/SiGe MOSFET devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure and device processing on gate oxide leakage characteristics are analysed in detail. We show that at high oxide electric fields where gate leakage is dominated by F-N tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. However for device operating regimes at lower oxide electric fields Poole-Frenkel (P-F) emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Consequently advanced strained Si/SiGe devices are inadvertently subject to a potential trade-off between power consumption (gate leakage current) and device reliability (gate oxide interface quality).

NBTI Effects in pMOSFETS with TiN/Hf-Silicate Based Gate Stacks

Effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSixOy (20% SiO2) based high-k gate stacks are studied under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (Delta VT) is most probably due to the mixed degradation within the bulk high-k. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of Delta VT in our devices conform to SiO2 based reaction-diffusion (R- D) model of NBTI. Under high bias condition at elevated temperatures higher Si-H bond-annealing/bond-breaking ratio, due to the experimentally observed absence of the impact ionization induced hot holes at the interracial layer (IL)/Si interface, probably limits the interface state generation and Delta VT as they quickly tend to saturate.

Anomalous BTI effects in n-type integrated power transistors

A novel bias-temperature-instability effect is observed in n-type integrated power transistors. The effect is enhanced by the total internal temperature of the device as well as by the oxide electric field. The total temperature that the device is experiencing is the sum of the ambient temperature and the temperature increase due to power dissipation. The latter is found to be the dominant effect in power transistors integrated in deep submicrometer technologies. A model is presented to calculate the safe operating area of the transistors.

Investigation of NBTI Recovery During Measurement

AbstractIn this work we present a rigorous investigation of the negative bias temperature instability (NBTI) recovery process during measurement intervals in comparison to the numerical solution of an extended reaction-diffusion (RD) model. In contrast to previous work, the RD model has been implemented in a multi-dimensional device simulator and is solved self-consistently together with the semiconductor device equations. This allows us to directly use many commonly approximated quantities such as the oxide electric field and the interface hole concentration in a self-consistent manner. In addition, the influence of the trapped charges can be more accurately considered by using a distributed Shockley-Read-Hall interface trap-charge model which has been coupled to the RD model. Thus, due to the self-consistent solution procedure, also the feedback of these charged interface-states on the Poisson equation is considered which influences the observed threshold voltage shift. Experimental data confirm the model which has been calibrated to a wide range of temperatures using a single set of parameters.

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current (SILC) through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress (CVS). The simulation results show that the SILC is formed by trap-assisted tunnelling (TAT) process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

Reaction-dispersive proton transport model for negative bias temperature instabilities

Negative bias temperature instabilities in p-channel metal-oxide-semiconductor field effect transistors are modeled by taking into account the generation of Pb0 centers at the (100)Si∕SiO2 interface, followed by the dispersive transport of protons away from the interface. It is shown that the characteristic time, oxide electric field, and temperature dependence of the threshold voltage shifts observed in these devices can be very well reproduced by the model. The general belief that the transport of positively charged species cannot explain negative bias temperature instabilities thus appears to be incorrect.

HYDROGEN AT THE Si/SiO2 INTERFACE: FROM ATOMIC-SCALE CALCULATIONS TO ENGINEERING MODELS

Two contrasting behaviors have been observed for H in Si / SiO 2 structures: a) Radiation experiments established that protons released in SiO 2 migrate to the Si / SiO 2 interface where they induce new defects; b) For oxides exposed first to high-temperature annealing and then to molecular hydrogen, mobile positive charge believed to be protons can be cycled to and from the interface by reversing the oxide electric field. First-principles density functional calculations identify the atomic-scale mechanisms for the two types of behavior and conditions that are necessary for each. Using the results of the atomic-scale calculations we develop a model for enhanced interface-trap formation at low dose rates due to space charge effects in the base oxides of bipolar devices. We find that the hole trapping in the oxide cannot be responsible for all the Enhanced Low-Dose-Rate Sensitivity (ELDRS) effects in SiO 2, and the contribution of protons is also essential. The dynamics of interface-trap formation are defined by the relation between the proton mobility (transport time of the protons across the oxide) and the time required for positive-charge buildup near the interface due to trapped holes. The analytically estimated and numerically calculated interface-trap densities are found to be in very good agreement with available experimental data.

The role of localized states in the degradation of thin gate oxides

A model is proposed to address the effects of oxide electric field and anode bias, as well as the role of hydrogen, in the trap generation process. The oxide wear-out phenomenon is considered as a multi-step process initiated by the capture of injected electrons by localized states in SiO 2. The captured electrons significantly weaken the corresponding Si–O bond, which becomes unstable with respect to the applied electric field and temperature. The hydrogen present in the oxide (due to the anode hydrogen release process) prevents restoration of the broken bonds and leads to the generation of neutral E′ centers. The model describes the charge-to-breakdown dependence on the electron energy, electric field, temperature, and oxide thickness.

Model of leakage current induced by dynamic stress in thin EEPROM tunnel oxides

It has been currently observed that Fowler–Nordheim tunneling injection through thin SiO 2 oxide layers (5–10 nm) induces leakage currents called stress-induced leakage currents (SILC). These could contribute to data retention loss in EEPROM non-volatile memory devices. In this work, we have stressed 7 nm thick SiO 2 MOS capacitors with bipolar symmetrical pulses similar to write–erase cycles used for EEPROM cell programming. I( V), current–voltage data, have been analyzed to identify the induced conduction mechanisms after different stress levels. It has been shown that I( V) data present two zones. The first zone, for oxide electric fields greater than 7 MV cm −1, always remains governed by a classical Fowler–Nordheim effect. At smaller electric fields corresponding to the SILC domain, the current has been successfully modelled by a trap-assisted conduction mechanism. At largest injected charge levels, coulombic attractive traps generated in SiO 2 overlap inducing conduction enhancement that we have described by a two-traps model.

On the electrical monitor for device degradation in the CHISEL stress regime

This paper reports a complete characterization of hot carrier-induced degradation in the CHannel Initiated Secondary ELectron (CHISEL) regime covering a large set of different stress bias conditions. Using several physical and electrical parameters, our results demonstrate that in the CHISEL regime, differently from the channel hot electrons case, the device degradation is univocally related to the gate current independently of the drain, source, substrate bias, and of the oxide electric field. The gate current is thus identified as the electrical monitor for device degradation in the CHISEL stress conditions.

New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs

In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS biased at V/sub G/>V/sub D/. We observe that the time-to-BD is strongly reduced in the hot carrier regime and that although the channel hot-electron injection into the oxide occurs mainly at the drain side, stress-induced leakage current (SILC) generation and oxide BD always occur at the source side. The results of these measurements indicate that not solely the energy of the injected electrons but also the oxide electric field is determinant in the oxide BD process.

A simple quantum model for the MOS structure in accumulation mode

A simple model for the accumulation mode of a MOS structure is proposed. The model regards the ground quantum level and is based on the approximated empirical expression for the band profile in semiconductor. The results for the dependency of a surface potential on the electric field in oxide were screened with the exact self-consistent solution and shown to be in a satisfactory agreement with it.

Capacitance and current-voltage simulation of EEPROM technology highly doped MOS structures

In this work, experimental capacitance (C–V) and current–voltage (I–V) data of electrically erasable programmable read-only memories (EEPROM) technology MOS structures were simulated. A specific test structure called a double-poly MOS capacitor reproducing the different stacked layers of an EEPROM cell state transistor has been used (7.2 nm SiO2 oxide, highly doped n+ substrate). Our aim was to research the most relevant model that allows a reliable extraction of electrical parameters and that could be easily introduced in industrial EEPROM devices simulators. To simulate C–V data, different classical and quantum models for the estimation of the semiconductor charge have been considered. Due to the substrate high-doping level and to the occurrence of Fowler–Nordheim (FN) injection, the available voltage domain for C–V recordings is reduced, which does not allow to distinguish between the different theoretical models predictions. I–V data were simulated using the classical FN model in which the oxide electric field–gate voltage relationship was extracted from the different C–V models mentioned above. Moreover, an iterative procedure we have proposed in a previous study has also been considered. It is shown that all the models lead to very comparable I–V simulations. These results let us conclude that the very time-consuming resolution of Schrodinger–Poisson coupled equations in a complete quantum approach is not necessary and that classical models remain sufficiently precise and reliable.

Experimental Determination of Ultrathin Oxide Thickness Using Conventional Capacitance–Voltage Analysis

The gate dielectric thickness can be determined by using the thickness-independent relationship between effective semiconductor thickness (Ts) and oxide electric field (Eox). The method based on the experimental Ts–Eox relationship offers both simplicity and accuracy for the evaluation of various oxide thicknesses, even though the capacitance–voltage (C–V) curve is abnormally distorted due to large leakage current. Using this simple C–V method, it is possible to estimate oxide thicknesses of less than 12 Å.

Constant charge erasing scheme for flash memories

This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated.

A model for gate oxide wear out based on electron capture by localized states

A model is proposed which addresses the effects of the oxide electric field and anode bias as well as the role of hydrogen in the trap generation process. The oxide wear-out phenomenon is considered as a multistep process initiated by the capture of injected electrons by localized states in SiO2. The captured electron significantly weakens the corresponding Si–O bond, which becomes unstable with respect to the applied electric field and temperature. The hydrogen presented in the oxide (due to anode hydrogen release process) prevents restoration of the broken bond that leads to the generation of a neutral E′ center. The model describes the charge-to-breakdown dependence on the electron fluence and energy, electric field, temperature, and oxide thickness.

A percolation based dielectric breakdown model with randomic changes in the dielectric constant

We describe a percolation based model for the dielectric breakdown of metal-oxide-semiconductor capacitors where the dielectric constant varies randomly throughout the oxide layer. We consider the SiO 2 oxide within a rectangular lattice framework, and the breakdown is simulated as a cluster growth depending process where the local electric field is a function of the randomly varying permissivity. The effects of the bias polarity, oxide film thickness and electric field strength are discussed. We obtain that the slope of the Weibull distribution increases with the oxide thickness, which agrees with experimental results. Additionally, the oxide reliability as function of the electric field intensity can only be simulated using a percolative model if the electric field is considered to be local, i.e., the oxide is a conductor locally.

Electric bidirectional stress effects on metal–oxide–silicon capacitors

Bidirectional electron injections were performed in thick and thin oxides of metal–oxide–silicon capacitors under a constant oxide electric field. Results show that dissymmetry, due to electron trapping near both oxide interfaces, is accentuated when the oxide is thin. However electron trapping is more marked when oxide is thick. Two kinds of thick oxide were used: wet and dry technologies. Wet oxide contains relatively more defects than dry. This is due to hydrogen incorporation in wet oxide during the oxidation process. But this difference is not well marked, because boron atoms injected after the oxidation process would deactivate hydrogen atoms. We describe the electron trapping by a well-known power law. The exponent of this law depends on oxide field polarity and also on oxide thickness but is technology independent. Results also show a nonexpecting behavior of tunneling current during bidirectional stress at a constant voltage. Here, we describe its causes and effects.