Oversampling Ratio Research Articles

Chiller fault detection and diagnosis by knowledge transfer based on adaptive imbalanced processing

The existing fault detection and diagnosis (FDD) model of chillers requires considerable normal and fault data. The acquisition of these data is time-consuming and expensive, and the model is only suitable for special units, which makes it difficult to popularize FDD technology in the operation and management of chillers. At present, a 120-ton chiller has only a small amount of normal and fault data when compared with the abundant data of a 200-ton model of the same series. This study investigates the FDD model of a 120-ton chiller and considers similar characteristics of the refrigeration cycle of the same series of chillers. A training set can be created using the 200-ton prior-knowledge data and the 120-ton data. However, this training set is imbalanced, and the common imbalanced processing synthetic minority oversampling technique (SMOTE) synthesis mechanism has an overlap problem. This study adopts two adaptive imbalance processing technologies called the adaptive synthetic sampling approach (ADASYN) and borderline SMOTE (BSM) that can solve the imbalance problem and SMOTE oversampling overlap problem during knowledge transfer. A support vector machine FDD model with 100% to 400% oversampling ratios is established. The best model is ADASYN with less than 100% oversampling ratio, with a diagnostic accuracy rate of 94.33%.

A low-power second-order sigma-delta modulator for MEMS digital geophones

This paper presents a low-power second-order sigma-delta modulator (SDM) for micro-electromechanical systems (MEMS) digital geophones (DGPs). The proposed SDM optimizes the performance of the first stage integrator and uses an adaptive class-AB current recycling operational transconductance amplifier (OTA) to improve the current efficiency. In addition, gain-enhancing circuits are applied in the OTA to increase the DC gain, and the chopper technique is used in the first stage integrator to reduce the flicker noise. The proposed SDM was implemented in the SMIC 0.18 μm CMOS technology and occupies an area of 0.82 mm2. The simulation results reveal the signal-to-noise ratio (SNR) was 76.46 dB and the effective number of bit (ENOB) was 12.4 bits. Measurements show that the SNR was 57.5 dB and the ENOB was 9.26 bits with a sampling rate of 256 kHz, an oversampling ratio 128, and a signal bandwidth of 1 kHz. The proposed SDM has a supply voltage of 1.8 V and a power consumption of 193.5 μW, which is suitable for the low-power MEMS DGPs applications.

36 μW fourth order sigma-delta modulator using single operational amplifier

ABSTRACT This paper presents a single loop fourth-order Discrete-Time Sigma-Delta Modulator (ΣΔM) using single Operational Amplifier (Op-Amp). Proposed ΣΔM utilises delay-based discrete-time integrators and an Op-Amp to implement all the integrators. Op-Amp reuse helps in saving power. A switched-capacitor based proposed design is simulated in standard 180 nm CMOS technology with an effective resolution of 12.04 bits. The proposed ΣΔM achieves a Signal to Noise Distortion Ratio (SNDR) of 74.24 dB with 78 dB of Dynamic Range (DR). An input signal of −4 dBFS magnitudes and 1.125 kHz of frequency is sampled at a sampling frequency of 320 kHz. The proposed circuit is designed for 10 kHz Bandwidth (BW) with Oversampling Ratio (OSR) of 16. The proposed modulator achieves Figure-of-Merit (FOM) of 158.68 dB/0.427 (pJ/conversion-step) with a total power consumption of 36 µW at 1.8 V supply voltage. The layout area of the proposed circuit is 134 µm ×134 µm.

Suppression of Spatial and Temporal Noise in a CMOS Image Sensor

This paper presents methodologies for suppressing the spatial and the temporal noise in a CMOS image sensor (CIS). First of all, it demonstrates by using a longer-length column bias transistor, both the fixed pattern noise (FPN) and temporal noise can be suppressed. Meantime, it employs column-level oversampling delta-sigma ADCs to suppress temporal noise as well as to facilitate the realization of the thermal compensation of dark signal non-uniformity (DSNU). In addition, the image pixels are re-configured as temperature sensors with inaccuracies within ±0.65 °C, between −20 and 80 °C. If the dark current and its non-uniformities are caused by thermal gradients, the obtained in-pixel thermal information can be employed to compensate for the measured dark current by 95 % and DSNU, up to 13 %. All the column-level 13 bit 2nd-order incremental delta-sigma ADCs are measured with SNR around 65 dB and INL around 1.5 LSB, when tested with a −8 dB input signal and sampling at 2 MHz with an oversampling ratio (OSR) of 128, when the full scale voltage is 2 Vp-p. The 4T Pinned Photodiode (PPD) CIS is measured to have a temporal noise of $34~\mu \text{V}$ rms (with an OSR of 128, or, an input referred temporal noise of 0.5 e− rms, with a conversion gain, CG, of $73~\mu \text{V}/ \text{e}^{-}$ ), a column gain FPN of 0.06 %, a dynamic range (DR) of 92 dB (with OSR = 512), as well as a linearity of 1 %. It has a measured DSNU of 3.2 %, after the thermal compensation using the in-pixel temperature sensors, a dark current of 290 pA/cm2 and 15 pA/cm2, measured at 60 °C, before and after the thermal compensation, respectively.

4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit

This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta-sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process. In view of area efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g' <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m1</sub> - 1) x A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master-slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits-at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.

A Study on Calculating Over-sampling Ratio using Classification Complexity

A Study on Calculating Over-sampling Ratio using Classification Complexity

A Low-power Extended-counting Delta-sigma ADC for CMOS Image Sensors

This paper presents an incremental delta sigma analog to digital converter (ADC) using an extended counting technique for CMOS image sensors. A modified extended counting method is proposed to reduce the over sampling ratio (OSR) and consequently increase conversion speed without increasing the hardware complexity. To further reduce the chip size and power consumption, a self-biased amplifier is shared between the adjacent stages of the delta-sigma modulator. The proposed ADC is fabricated in a 0.18-㎛ CMOS image sensor process and occupies 0.0026 ㎟. It achieves 65 ㏈ of signal noise and distortion ratio (SNDR) for a signal bandwidth of 156.25 ㎑ with a 20 ㎒ operating clock and consumes 45 μW from a 1.8 V power supply. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / −0.22 and +0.61 / −0.64 LSB (least significant byte), respectively.

A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator

This brief presents a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a lossless integrator for achieving low power and high NS efficiency. It implements the lossless integrator through a ping-pong structure and a low-gain dynamic amplifier with moderate gain variation tolerance. Taking advantage of the lossless integrator, a low resolution SAR ADC is allowed under the same quantization noise budget. Fabricated in a 65-nm CMOS process, the prototype 8-bit NS-SAR ADC consumes 1.24 mW at 1.2 V while operating at 100 MS/s. It achieves a peak signal to noise and distortion ratio (SNDR) of 77 dB over a bandwidth of 3.125 MHz at the oversampling ratio (OSR) of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.

A 102.2-dB, 181.1-dB FoM Extended Counting Analog-to-Digital Converter With Capacitor Scaling

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline architecture which breaks the speed bottleneck of the existing SAR or SAR-assisted-type NS analog-to-digital converters (ADCs). Rather than only for residue amplification and pipeline operation, the multiplying digital-to-analog converter (MDAC) is also reused as unity buffer and analog adder to realize the NS with error feedback (EF) structure in this design. While incorporating the proposed alternative loading capacitor (ALC) technique, an ideal first-order noise transfer function (NTF) is realized without additional feedback phase and only with a small analog circuit overhead. Unlike other NS SAR ADCs that involved amplification, the inter-stage gain attenuates the noise from the second-stage comparator, thus leading to both high speed and resolution. Fabricated in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.1 dB over 12.5-MHz bandwidth (BW) with only over-sampling ratio (OSR) of 8. Under a 1.2-V supply voltage, the ADC consumes 4.5 mW and exhibits a Scherier figure of merit (FoM) of 171.5 dB.

A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator

ABSTRACTThis paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2. The energy required per conversion step is 0.4 pJ/conv.

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Reconstruction of missing information in diffraction patterns and holograms by iterative phase retrieval

It is demonstrated that an object distribution can be successfully retrieved from its diffraction pattern or hologram, even if some of the measured intensity samples are missing. The maximum allowable number of missing values depends on the linear oversampling ratio σ, where the higher the value of σ, the more intensity samples can be missing. For a real-valued object, the ratio of missing pixels to the total number of pixels should not exceed (1 - 2/σ2) or (1 - 1/σ2) in the acquired diffraction pattern or hologram, respectively. For example, even 5% of the measured intensity values at an oversampling ratio of σ=8 are sufficient to simultaneously retrieve the object distribution and the missing intensity values. It is important that the missing intensity values should not be concentrated in the centre, but should be randomly distributed over the acquired diffraction pattern.

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

This study focuses on the design of a 2-1 switched-current (SI) multi-stage noise-shaping delta–sigma modulator with a digital noise-cancellation circuit. The noise-cancellation circuit is designed by employing various algorithms for designing the logic circuits and constructing a delay block with an inverter and a transmission gate. It can eliminate the higher-order quantisation noise from the first stage of the modulator completely. In the proposed differential current-mode sample-and-hold circuit, low-input impedance is presented with feedback and width-length adjustment in SI feedback memory cell, a coupled differential replicate with the common-mode feed-forward (CMFF) circuit is used to stabilise the common-mode bias voltage at input terminal, and a differential cross-connected CMFF circuit is utilised to fix the bias voltages. Post-layout simulations reveal that the simulated signal-to-noise-and-distortion ratio (SNDR) was 90.4 dB and the effective number of bit (ENOB) was 14.73 bits. Measurements show that the SNDR was 59.13 dB and the ENOB was 9.53 bits at a sampling rate of 10.24 MHz, an oversampling ratio of 256, and a signal bandwidth of 20 kHz. This design has a power requirement of 12.99 mW from a supply voltage of 1.8 V and occupies a core area of 0.14 mm2.

Noise transfer function design for delta-sigma modulators using the Gegenbauer polynomial

Abstract An efficient noise transfer function (NTF) is central to the design of a delta-sigma modulator (DSM). A popular method for designing an NTF is based on the placement of its zeros optimally in the frequency band of interest such that the in-band energy is minimized. The poles of the NTF, however, are those of a maximally-flat all-pole filter. The limitation of this method is that when the oversample ratio (OSR) of the DSM is low, the 3-dB cutoff frequency of the denominator polynomial of the NTF may approach the edge of the passband of the NTF. This causes the zeros to no longer be optimal. In this paper, we present a method of designing an NTF based on the Gegenbauer polynomial which does not have this limitation. We show that the signal-to-quantization noise ratio (SQNR) of the NTFs designed with our method is significantly better than that of the NTFs designed using the well-known method.

Parameter optimization for 3D-reconstruction from XFEL diffraction patterns based on Fourier slice matching.

Single-particle analysis (SPA) by X-ray free electron laser (XFEL) is a novel method that can observe biomolecules and living tissue that are difficult to crystallize in a state close to nature. To reconstruct three-dimensional (3D) molecular structure from two-dimensional (2D) XFEL diffraction patterns, we have to estimate the incident beam angle to the molecule for each pattern to assemble the 3D-diffraction intensity distribution using interpolation, and retrieve the phase information. In this study, we investigated the optimal parameter sets to assemble the 3D-diffraction intensity distribution from simulated 2D-diffraction patterns of ribosome. In particular, we examined how the parameters need to be adjusted for diffraction patterns with different binning sizes and beam intensities to obtain the highest resolution of molecular structure phase retrieved from the 3D-diffraction intensity. We found that resolution of restored molecular structure is sensitive to the interpolation parameters. Using the optimal parameter set, a linear oversampling ratio of around four is found to be sufficient for correct angle estimation and phase retrieval from the diffraction patterns of SPA by XFEL.

Table‐based PWM for all‐digital RF transmitters

SummaryIn this paper, a novel pulse‐width modulator (PWM) for an all‐digital PWM transmitter based on switching amplification is presented. In this approach, each symbol is represented by a sequence of pre‐computed PWM pulse widths stored in a table that results in reduced error vector magnitude (EVM). A high‐resolution pulse former is then used to build the bipolar radio frequency (RF) signal. Simulations and comparisons to other approaches reported in the literature under different oversampling ratios and finite time resolutions are presented. The impact of nonlinearities in the variable duty‐cycle generator is also analyzed to demonstrate the robustness of the proposed technique.

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

The noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the $\Delta \Sigma $ ADC. Most prior works adopting the cascaded integrator feed-forward (CIFF) structure demonstrate inefficiency in realizing optimized noise transfer function (NTF). This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR. It implements a low-power scaling-friendly EF path by using a passive finite impulse response (FIR) and a comparator-reused dynamic amplifier with process-voltage-temperature (PVT) tracking background calibration. Fabricated in 40-nm CMOS, the prototype chip consumes $84~\mu \text{W}$ when operating at 10 MS/s. The NS-SAR achieves peak Schreier FoM of 178 dB with 79-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

A 0.13-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu\text{m}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; CMOS SoC for Simultaneous Multichannel Optogenetics and Neural Recording

This paper presents a 0.13- $\mu \text{m}$ CMOS system-on-chip (SoC) for simultaneous multichannel optogenetics and multichannel neural recording in freely moving laboratory animals. This fully integrated system provides 10 multimodal recording channels with analog-to-digital conversion and a four- channel LED driver circuit for optogenetic stimulation. The bio-amplifier design includes a programmable bandwidth (BW) (0.5 Hz–7 kHz) to collect either the action potentials (APs) and/or the local field potentials (LFPs) and has a noise efficiency factor (NEF) of 2.30 for an input-referred noise of 3.2 $\mu V_{\text {rms}}$ within a BW of 10–7 kHz. The low-power delta–sigma ( $\Delta \Sigma $ ) MASH 1-1-1 analog-to-digital converter (ADC) is designed to work at low oversampling ratios (OSRs) (≤50) and has an effective number of bits (ENOB) of 9.75 bits at an OSR of 25 (BW of 10 kHz). The utilization of a $\Delta \Sigma $ ADC is the key to address the flexibility needed to address different noise versus power consumption tradeoff of various experimental settings. It leverages a new technique that reduces its size by subtracting the output of each $\Delta \Sigma $ branch in the digital domain, instead of in the analog domain as done conventionally. The ADC is followed by an on-chip fourth-order cascaded integrator-comb (CIC4) decimation filter (DF). A whole recording channel, including the bio-amplifier, the $\Delta \Sigma $ MASH 1-1-1, and the DF consumes 11.2 $\mu \text{W}$ . Optical stimulation is performed with an LED driver using a regulated cascode current source with feedback that can accommodate a wide range of LED parameters and battery voltages. The SoC is validated in vivo within a wireless experimental platform in both the ventral posteromedial nucleus (VPM) and cerebral motor cortex brain regions of a virally mediated Channelrhodopsin-2 (ChR2) rat.