Overlay Targets Research Articles

Neural network driven sensitivity analysis of diffraction-based overlay metrology performance to target defect features

Overlay (OVL) is one significant performance indicator for the lithography process control in semiconductor manufacturing. The accuracy of the OVL metrology is extremely critical for guarantee the lithography quality. Currently, diffraction-based overlay (DBO) is one of the mainstream OVL metrology techniques. Unfortunately, the accuracy of the DBO metrology is largely affected by the defect features of the OVL target. Therefore, there is a strong need to investigate the impacts of these target defects on the DBO metrology performance. However, efficiently investigating the statistical and interactive impacts of various DBO target defects remains challenging. This study aims to address this issue through proposing an intelligent sensitivity analysis approach. A cumulative distribution based global sensitivity analysis (GSA) method is utilized to assess the nonlinear influences of multiple defects in the OVL target on the DBO inaccuracy. The scenarios with both known and unknown distributions of the OVL target defects are considered. For the former, a neural network driven forward model is constructed for fast calculating the optical diffraction responses to accelerate the GSA process. For the latter, another neural network based inverse model are built for efficiently estimating the distribution of the target defects. Finally, a series of simulation experiments are conduct for typical DBO targets with multiple common defect features. The results demonstrate the effectiveness and robustness of the proposed approach as well as give valuable insights into the DBO defect analysis. Our study provides a strong tool to assist the practitioners in achieving intelligent and efficient DBO analysis and thus in enhancing OVL metrology performance.

Mitigating the Impact of Asymmetric Deformation on Advanced Metrology for Photolithography

Controlling overlay in lithography is crucial for improving the yield of integrated circuit manufacturing. The process disturbances can cause undesirable morphology changes of overlay targets (such as asymmetric grating), which can significantly impact the accuracy of overlay metrology. It is essential to decouple the overlay target asymmetry from the wafer deformation, ensuring that the overlay metrology is free from the influence of process-induced asymmetry (e.g., grating asymmetry and grating imbalance). Herein, we use an asymmetric grating as a model and show that using high-diffraction-order light can mitigate the impact of asymmetric grating through the rigorous coupled-wave analysis (RCWA) method. In addition, we demonstrate the diffraction efficiency as a function of the diffraction order, wavelength, and pitch, which has guiding significance for improving the measurement accuracy of diffraction-based overlay (DBO) metrology.

X-ray-based overlay metrology using reciprocal space slicing analysis

Overlay serves as the pivotal performance indicator for lithography tools, and its prompt and precise measurement significantly underpins the process yield control. At present, diffraction-based overlay metrology employing optical wavelengths encounters constraints in terms of measurement sensitivity. When transitioning to x-ray wavelengths, the critical-dimension small-angle x-ray scattering (CDSAXS) method for nanostructure characterization necessitates reciprocal space mapping (RSM) and inverse problem solving, resulting in substantial throughput constraints. In this work, we propose an x-ray-based overlay metrology using reciprocal space slicing analysis (RSS), yielding high-precision overlay measurement at one single angle of incidence (AOI). Moreover, we examine the robustness of the proposed method against errors stemming from overlay target grating fabrication and measurement processes, substantiating its efficacy as a novel x-ray-based overlay metrology and unveiling the potential application of x-ray-based techniques within the realm of integrated circuit metrology.

Multi-spectral snapshot diffraction-based overlay metrology.

Diffraction-based overlay (DBO) metrology has been successfully introduced to deal with the tighter overlay control in modern semiconductor manufacturing. Moreover, DBO metrology typically needs to be performed at multiple wavelengths to achieve accurate and robust measurement in the presence of overlay target deformations. In this Letter, we outline a proposal for multi-spectral DBO metrology based on the linear relation between the overlay errors and the combinations of off-diagonal-block Mueller matrix elements ΔM = Mij - ( - 1)jMji (i = 1, 2; j = 3, 4) associated with the zeroth-order diffraction of overlay target gratings. We propose an approach that can realize snapshot and direct measurement of ΔM over a broad spectral range without any rotating or active polarization component. The simulation results demonstrate the capability of the proposed method for multi-spectral overlay metrology in a single shot.

Designing Highly Precise Overlay Targets for Asymmetric Sidewall Structures Using Quasi-Periodic Line Widths and Finite-Difference Time-Domain Simulation.

The present study introduces an optimized overlay target design to minimize the overlay error caused by asymmetric sidewall structures in semiconductor manufacturing. To achieve this goal, the overlay error formula was derived by separating the asymmetric bottom grating structure into symmetric and asymmetric parts. Based on this formula, it was found that the overlay target design with the linewidth of the bottom grating closed to the grating period could effectively reduce the overlay error caused by the sidewall asymmetry structure. Simulation results demonstrate that the proposed design can effectively control the measurement error of different wavelengths within ±0.3 nm, even under varying sidewall angles and film thicknesses. Overall, the proposed overlay target design can significantly improve the overlay accuracy in semiconductor manufacturing processes.

Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

Image-based overlay target design using a grating intersection

Background: An overlay target design is essential before performing overlay metrology and has a great impact on overlay performance. In addition, accurate overlay metrology is required to achieve high product yields in semiconductor manufacturing. When asymmetry of the overlay target occurs, it is necessary to increase the area of the pattern existing in the target and stabilize the optical aberration for stable measurement. For this reason, we propose an image-based overlay target design that can secure a larger area compared with the existing overlay target and stabilize the optical aberration by overlapping and exposing the upper and lower patterns of the overlay target.Aim: The effective area of the existing mark design is improved by proposing an overlay target and a measurement method used in image-based overlay measurement.Approach: The proposed overlay target design is configured by arranging different marks orthogonally to the upper and lower layers, and different two-dimensional information can be inserted in the same area. When necessary, single-dimensional information desired by the user can be obtained through a technique called projection, and it has the advantage of using a larger effective area than the existing overlay target.Results: Overlay can be measured using projected signal components, and the possibility and performance of the proposed target can be confirmed through simulation and test wafer. In addition, it was possible to bring about a 15% improvement in total measurement uncertainty performance compared with the existing advanced imaging metrology (AIM) target by taking a wider effective area.Conclusions: An overlay target design is proposed to solve the technical problems of the existing overlay target design. The proposed overlay target has a method that is capable of minimizing the size of the overlay target while maximally maintaining the signal density, a way of reducing the influence of aberration, and various other advantages.In addition, the proposed method provides a design rule that breaks the “lower pattern and upper pattern must not overlap” framework.

Calibration-based overlay sensing with minimal-footprint targets

Overlay measurements are a critical part of modern semiconductor fabrication, but overlay targets have not scaled down in the way devices have. In this work, we produce overlay targets with very small footprint, consisting of just a few scattering nanoparticles in two separate device layers. Using moiré patterns to deterministically generate many overlay errors on a single chip, we demonstrate readout of the relative displacement between the two layers and show that calibration on one realization of the targets can be used for overlay measurements on subsequent instances. Our results suggest that using greater quantities of smaller overlay targets may benefit performance both directly and through finer sampling of deformation.

Diffraction-based overlay metrology using angular-multiplexed acquisition of dark-field digital holograms.

In semiconductor device manufacturing, optical overlay metrology measures pattern placement between two layers in a chip with sub-nm precision. Continuous improvements in overlay metrology are needed to keep up with shrinking device dimensions in modern chips. We present first overlay metrology results using a novel off-axis dark-field digital holographic microscopy concept that acquires multiple holograms in parallel by angular multiplexing. We show that this concept reduces the impact of source intensity fluctuations on the noise in the measured overlay. With our setup we achieved an overlay reproducibility of 0.13 nm and measurements on overlay targets with known programmed overlay values showed good linearity of R2= 0.9993. Our data show potential for significant improvement and that digital holographic microscopy is a promising technique for future overlay metrology tools.

Uncertainty Estimation and Design Optimization of 2D Diffraction-Based Overlay Metrology Targets

Scatterometry is an optical metrology technique in which light scattered from a specifically designed grating stack (overlay target) is measured in the far-field. Using 1D periodic overlay target designs, the technique has been shown to have nanometer-scale sensitivity to spatial misalignments of subsequent patterned layers, which are also known as overlay errors. However, while scatterometry is highly sensitive to overlay errors, multiple sources of systematic errors hinder its absolute accuracy. Here, we investigate how an extended version of scatterometry called Fourier scatterometry, in combination with more complex overlay target designs, can help addressing those challenges. To this end, we developed a statistical method that can determine the influence of 2D overlay targets on the overlay measurement uncertainty. We study periodic and deterministic aperiodic designs as well as designs that emerged from simulated annealing optimizations. Our results suggest that current overlay target designs could be augmented by more complex 2D designs to fulfill specific purposes, such as fabrication robustness and high sensitivity over a large overlay range.

Enhancement of Diffraction-Based Overlay Model for Overlay Target With Asymmetric Sidewall

Overlay metrology is crucial to process control in manufacturing semiconductor devices. Diffraction-based overlay (DBO) is an effective overlay measurement approach because it exhibits multiple advantages. This study analyzed measurement errors caused by sidewalls in the bottom gratings of DBO targets. Accordingly, improvement was proposed using a neural network. First, rigorous coupled wave analysis was employed to calculate the pupil images generated by an overlay target. These images were then used as a data set. Next, two-directional twodimensional principal component analysis was used to reduce the dimension of features in these images. The features were then used to train a neural network and determine weighting coefficients in each network layer to create a DBO model. This study used virtual metrology to analyze 30 types of overlay targets and generated 18900 pupil images to create a data set. Each overlay target model was measured 10 times, and shot noise, dark noise, and quantization noise in the pupil images were accounted for. The simulation results revealed that when the dose level was 1000 mJ/s·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the overlay mean square error of the testing data was 0.40nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , indicating notable improvement in the measurement results of overlay targets with bottom grating sidewalls. Therefore, the proposed neural network-based DBO model can be applied to overlay targets with sidewalls and effectively improve the overlay accuracy.

Multiobjective optimization for target design in diffraction-based overlay metrology.

Overlay target design is an important issue in overlay metrology, whose aim is to probe the optimal overlay target to achieve good performance on measurement precision and accuracy even in the presence of process variation. In this paper, the target design problem is first formulated as a multiobjective optimization problem and then solved by the multiobjective genetic algorithm. The feasibility of the proposed method is verified based on simulations carried out on two overlay targets. The results reveal that measurements with high precision, accuracy, and process robustness could be achieved on the targets designed by the proposed method.

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

Device-correlated metrology for overlay measurements

One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Overlay measurements by Mueller polarimetry in back focal plane

Angle resolved Mueller polarimetry implemented as polarimetric imaging of a back focal plane of a high NA microscope objective has already demonstrated a good potential for CD metrology. Here we present the experimental and numerical results indicating that this technique may also be competitive for the measurements of overlay error δ. A series of samples of superimposed gratings with well controlled overlay errors have been manufactured and measured with the angle resolved Mueller polarimeter. The overlay targets were 20-μm wide. When the overlay error is δ is equal to 0, absolute values of elements of real 4×4 Mueller matrix M are invariant by matrix transposition. Otherwise this symmetry breaks down. Consequently, we define the following overlay estimator matrix as E = |M| − |M|t. The simulations show that matrix element E14 is the most sensitive to the overlay error. The scalar estimator of E14 was calculated by averaging the pixel values over a specifically chosen mask. This estimator is found to vary linearly with δ for overlay values up to 50 nm. Our technique allows entering small overlay marks (down to 5-μm wide). Only one target measurement is needed for each overlay direction. The actual overlay value can be determined without detailed simulation of the structure provided two calibrated overlay structures are available for each direction.

New approaches for scatterometry-based metrology for critical distance and overlay measurement and process control

mmunication between lithography and metrology is becoming increasingly demanding in advanced nodes. This is where the requirements for metrology become extremely tight. This work is dedicated to the search for clean metrology that is required to address these requirements. Metrology measurements are obtained via an angle-resolved scatterometry-based platform (called YieldStar). Details of the technology behind YieldStar were thoroughly discussed by Vanoppen et al. in 2010. In this current work, measurement limits are challenged to test resolution and measurement uncertainty for overlay, critical dimension (CD), and sidewall angle (focus). Results indicate an atomic-scale performance of deep subnanometers. Two different sizes of scatterometry-based overlay targets are evaluated and compared using a technique called the similarity index. A CD reconstruction model is tested for cross talk of underlying thin-film layers, specifically the case where one of the underlying layers is anisotropic. A systematic approach is taken to increase the complexity of a CD reconstruction model in steps to evaluate the capability of handling birefringence effects of anisotropic material in the model. CD metrology data (1-D and 2-D/hole layers) are compared to CD scanning electron microscope data. Focus measurements are also extended for product wafers, and focus precision is evaluated. In addition, CD metrology monitor wafer applications, such as hotplate monitoring and overlay metrology monitor wafer application for scanner stability and matched machine overlay, are tested.

Overlay Real-Time Video Multicast System

In this paper, we present an effective overlay real-time video multicast system over the Internet. The proposed system effectively integrates overlay multicast technology and video compression technology. Overlay multicast tree and target bit rate are determined to satisfy the given average delay constraint, and H.263+ rate control is implemented to enhance the human visual perceptual quality over the multicast tree. Finally, experimental results are provided to show the performance of the proposed overlay video multicast system over the Internet.

Accuracy of diffraction-based overlay metrology using a single array target

We focus on the capability and theoretical limits of a model-based scatterometry method to determine overlay using a single two-dimensional array target. We use our modeling capability to design an optimized test target for scatterometer-based overlay measurements in a range of semiconductor films. We propose a methodology to measure the overlay using a single two-dimensional array target designed with intentional offsets, x and y, between the top and bottom grid arrays along the X and Y directions. This method allows extraction of the two-dimensional overlays from first diffraction order measurements through bi-azimuth angle analysis (0 and 90 deg with respect to the incidence plane), and includes a simple linear response algorithm. Two critical issues are taken into account: correlation of x and y and lithography process errors. We have simulated the diffraction signatures of a two-dimensional target with a pitch of 400 nm and linewidth of 100 nm, and optimized the overlay target design to maximize the measurement sensitivity and minimize the correlation of two axial measurements. We also investigate the influence of parameter variations on overlay measurement error

Combinatorial overlay control for double patterning

The extension of optical lithography to 32 nm and beyond is dependent on double-patterning at critical levels. Double patterning adds degrees of freedom for overlay variation while reducing the allowed overlay tolerance. Overlay control requires the assessment and minimization of error among various mask/layer combinations. The possible overlay control combinations scale as Cn=(2n−1)2 with the number of reference layers n containing (x,y) alignment and overlay targets. Finding the optimum overlay control pathway requires that we employ the on-product means to examine multiple options compatible with the product overlay tolerances. The Blossom overlay target enables simultaneous determination of all combinations of patterns represented within the measurement tool field of view. We examine Blossom enabled use cases in double patterning overlay control as demonstrated at contact-to-gate registration on a 32 nm product.