Abstract
Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.
Highlights
As ground rules shrink, state-of-the-art integrated circuit production processes are always challenged to meet evertightening overlay error requirements
Special test wafers termed engineered stress monitor (ESM) wafers were used to assess the capability of the wafer shape data to predict process-induced overlay errors
Several specific ESM wafer types were used for the data presented
Summary
State-of-the-art integrated circuit production processes are always challenged to meet evertightening overlay error requirements. Another source of stress variation is film deposition, which is not perfectly uniform across the wafer High temperature processes such as rapid thermal anneal (RTA) tools can have nonuniform thermal profiles across the wafer which may lead to thermally induced nonuniform stress. In cases of severe thermal gradients at elevated temperature, silicon crystal planes can plastically yield or “slip,” resulting in both crystalline defects as well as overlay errors These stress variations result in wafer distortions which can limit overlay error capability. When pulled flat on an exposure tool chuck, the nonuniform stress will cause local magnification changes in the wafer, i.e., higher-order wafer in-plane distortion (IPD).
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