Output Rise Time Research Articles

An optically coupled power stimulus isolation unit with high voltage and fast rise time output.

Recent technological developments have created new devices that could improve and simplify the construction of stimulus isolators. HEXFET transistors can switch large currents and hundreds of volts in nanoseconds. The newer opto-isolators can give a pulse rise time of a few nanoseconds, with output compatible with MOSFET devices, in which delays are reduced to nanoseconds. Integrated DC/DC converters are now available. Using these new resources we developed a new electrical stimulus isolator circuit with selectable constant-current and constant-voltage modes, which are precise and easy to construct. The circuit works like a regulated power supply in both modes with output switched to zero or to free mode through an opto-isolator device. The isolator analyses showed good practical performance. The output to ground resistance was 10(11) ohms and capacitance 35 picofarads. The rise time and fall time were identical (5 microseconds) and constant. The selectable voltage or current output mode made it very convenient to use. The current mode, with higher output resistance values in low current ranges, permits intracellular stimulation even with tip resistances close to 100 megaohms. The high compliance of 200 V guarantees the value of the current stimulus. The very low output resistance in the voltage mode made the device highly suitable for extracellular stimulation with low impedance electrodes. Most importantly, these characteristics were achieved with a circuit that was easy to build and modify and assembled with components available in Brazil.

Development of 60 ps rise-time ferrite-loaded coaxialline

An experimental ferrite-loaded coaxial line-based pulse-sharpening system for repetitive operation and with output amplitudes of up to 20 kV into 50 Ω is described. Output rise-times are found to reduce with increasing pulse voltage, down to 60 ps at 20 kV. Principal features of the system are a multi-stage ferrite line design, axial magnetic biasing, and an oil dielectric/insulation layer. This system shows the potential of ferrite line pulse sharpeners for generating 50–100 ps rise-time pulses at 10–20 kV and upward.

Noise and speed characteristics of test transistors and charge amplifiers designed using a submicron CMOS technology

The analog characteristics of the industrial MIETEC 0.7 μm CMOS process have been measured using test transistors and a charge amplifier based on an Operational Transconductance Amplifier. The test transistors have been built with an aspect ratio W L = 7000 1 and tested in saturation at a drain current of 400 μA. In these conditions the 1 f corner noise frequency of the p-channel was measured at 2.5 kHz. A charge amplifier has been designed with an input p-channel transistor of 3500 μm 2 gate area. At a drain current of 400 μA, the noise measurements of the charge amplifier in ENC was 470 e − rms at 0 pF external capacitance, with a slope of 12 e − rms per pF, for a peaking time of 500 ns made by a CR-RC 2 filter. The output risetime was 13 ns at 0 pF. This promising mixed-mode technology enables the development of charge amplifiers and more complex analog circuits that can approach the noise performance of designs built with JFET transistors.

Electrooptic characterization of modulation-doped field-effect transistors with monolithically-integrated test fixtures

The authors report on the fabrication and electrooptic measurement of modulation-dopted field-effect transistors (MODFETs) monolithically integrated with coplanar stripline fixtures incorporating photoconductive switches. Both lattice-matched devices on InP substrates and pseudomorphic devices on GaAs substrates, as well as two different gate access structures have been characterized. In comparing two devices with identical gate access structures, one finds that the delay time of the pseudomorphic device is almost twice as long as that of the lattice-matched device. Surprisingly, the switching times (drain output risetimes) of the two devices are comparable. One also sees that the gate access structure significantly affects the switching in two lattice-matched devices: the switching times for double-gate and single-gate contact devices are 4.2 and 5.2 ps, respectively. In this case, however, no difference was seen in the delay times. These results show that, for the present devices, the switching and delay times are dominated by different mechanisms.

A low temperature co-fired ceramic land grid array for high speed digital applications

A Land Grid Array (LGA) package was designed and fabricated to utilize specific materials and design concepts for high speed operation. The performance of this LGA was compared with that of a functionally and dimensionally equivalent Pin Grid Array (PGA) that is currently being used to package high speed silicon ECL gate arrays. Two structures that were sources of signal degradation in the PGA, the pins and a layer of plating lines, were eliminated in the design of the LGA. The package was fabricated out of Du Pont Green Tape low temperature co-fired ceramic (LTCC) with gold conductors and vias. This combination of an improved LGA, structure and materials with superior high speed properties resulted in a package with improved performance and decreased signal degradation when compared with conventional high temperature co-fired ceramic (HTCC) PGAs. Time domain reflectometry measurements of the LGA, when compared with those of the equivalent PGA, showed less than half the deviation from a 50 /spl Omega/ characteristic impedance. A 'package risetime' performance factor, which describes the contribution the package makes to the output risetime, was calculated from time domain transmission (TDT) data. These results also showed significantly improved performance in the LGA. For the best line in the LGA, the package risetime was 104 ps, which is a 98% improvement over the equivalent line in the PGA. A ground delay effect due to the separation between the signal I/O and nearest ground I/O was observed. This effect, which increased with increasing signal-nearest ground I/O spacing, was seen to cause significant degradation and increased risetimes that should be avoided in high speed packages.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of a high-performance, low-noise charge preamplifier

A high-performance, low-noise charge preamplifier integrated circuit is designed and tested for the Superconducting Super Collider. The amplifier is fabricated in a new dielectrically isolated (DI), radiation-hardened, very-high-frequency (VHF) BIFET IC process technology from Harris Corporation. This new process provides n-p-n, p-n-p, and p-channel JFET devices which are both radiation-hardened, tested to 3 Mrad of total gamma ray exposure and 3*10/sup 14//cm/sup 2/ neutron dosage, and provides high-frequency performance. The new charge preamplifier provides improved performance with an output rise time of 65 ns, input inferred noise of 28.6 mu V, or 3575 electrons, and power dissipation less than 33.7 mW. The circuit design is discussed with attention given to those design characteristics needed to specifically accommodate low noise with the new radiation-hardened process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation and interpretation of fast rise time light-activated p-i-n diode switches

A simulation program and a comprehensive physical interpretation for risetimes and output powers of the long transit p-i-n diode under high and low optical-pulse excitations as well as at various impedances are presented. The physical interpretation explains the mechanisms of the switch risetime limitation in terms of the cancellation electric field due to separated photocarriers, the induced electric field with various RC time delays, and the optical-pulse energy risetime. Under high optical excitations and long circuit risetimes, the output risetime is determined only by the electric field cancellation time associated with the collapse of the total electric field and decreases with increasing optical-pulse excitation. This is in contrast to the case of low optical-pulse excitations where the risetime is determined by both the circuit risetime and the optical-pulse energy risetime.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A wide-band class-B video output driver

The authors describe a high-resolution class-B video output driver IC for analog or digital video display systems. The IC, which uses a single 5-V supply, is combined with high-voltage discrete output power transistors to drive either a color or a monochrome CRT (cathode ray tube). The system yields greater bandwidth while consuming one third the power required by conventional class-A CRT drivers. The circuit was fabricated in a 2- mu m oxide-isolated bipolar process with peak f/sub T/ approximately=8 GHz. Using discrete output transistors (f/sub T/=1 GHz, C/sub CB/=2pF), board testing on a CRT with a nominal 10-pF load yielded approximately 15-ns output rise and fall times with 45-V swing and 60-mA slew current limit. >

Anneling Effects on the Rise Time of Gamma-Ray Irradiated Au-Si Nuclear Detectors

Thermal annealing effects on silicon surface barrier nuclear detectors damaged with radiation are investigated by measuring output rise time and induced defect densities. Silicon wafers as materials of the detectors are irradiated with gamma-rays of 60-Co, and then the irradiated silicon specimens are annealed thermally. The rise time measurement for 241-Am alpha-particles incidence is performed by using a digital system. It is observed that the rise time of the annealed detectors becomes faster than that of the irradiated detectors. The induced defect densities, measured with DLTS method, are reduced to about 1/2 the amount of irradiated detectors, for annealing temperature 420K, 60 minutes. The characteristics of the detectors irradiated with less than l×107R are almost recovered in accordance with the decrease of defect densities.

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.

Pulse sharpening effects in ferrites

Pulse sharpening effects were investigated both experimentally and theoretically in a coaxial transmission line filled with commercially available magnesium manganese ferrite. Measurements of rise-time reduction as a function of pulse voltage, magnetic field bias, and line length were obtained. Output rise times were reduced to values as low as 2.0 ns, with incident rise times as high as 30 ns, operating at a source voltage of 10 kV. The experimental results agree with a model in which the ferrite line is treated as an equivalent transmission line in which the series inductance and resistance depend on the magnetization reversal. A potential application for the ferrite pulse sharpener is the combination of this device with a commercially available slower switch, which will provide kilovolt pulses with nanosecond rise times, operating at high pulse repetition rates.

Timing coincidence studies with fast photomultipliers

Abstract The time response of RCA C70045D photomultipliers was studied using a subnanosecond light flasher. The tubes, which have an output rise time of approximately 0.5 ns, were used in coincidence to study the variations in the fwhm of the time spectrum over a certain dynamic range of pulse amplitudes for both leading edge and constant fraction discrimination. A comparison has also been made for the measured time resolutions with some of the other fast photomultipliers.

An improved programmable delay line

A programmable delay line has been developed that makes use of microstrip transmission line and temperature compensated ECL gates. This instrument delays standard NIM pulses and has settings of 0–64.5 ns. The output risetime is ⋍ 1 ns, independent of the delay setting. The delay stability at maximum delay is ⋍ 130 ppm/ °C, which is better than for RG-55 B/U coaxial cable. The minimum pulse width is less than 3 ns, and the difference in pulse width between the output and the input is less than 150 ps. Design tradeoffs and performance measurements are described.

High frequency characteristics of meandering line-resistors with regard to the design of thin-film circuits : H. Grundner and H. Fechner. IERE Conf. Hybrid Microelectronics, Loughborough p. 63. 9–11 Sept. 1975

The analog characteristics of the industrial MIETEC 0.7 μm CMOS process have been measured using test transistors and a charge amplifier based on an Operational Transconductance Amplifier. The test transistors have been built with an aspect ratio WL = 70001 and tested in saturation at a drain current of 400 μA. In these conditions the 1f corner noise frequency of the p-channel was measured at 2.5 kHz. A charge amplifier has been designed with an input p-channel transistor of 3500 μm2 gate area. At a drain current of 400 μA, the noise measurements of the charge amplifier in ENC was 470 e− rms at 0 pF external capacitance, with a slope of 12 e− rms per pF, for a peaking time of 500 ns made by a CR-RC2 filter. The output risetime was 13 ns at 0 pF. This promising mixed-mode technology enables the development of charge amplifiers and more complex analog circuits that can approach the noise performance of designs built with JFET transistors.

Aluminum-silicon Schottky barriers as semiconductor targets for EBS devices

The ideal semiconductor target for EBS devices is most closely approximated by the Schottky barrier junction, with Al having the highest figure of merit. Accordingly, large area (1·27 mm 2), high-field Al nSi Schottky barrier junctions surrounded by a p- n junction guard-ring have been fabricated in unpassivated, SiO 2 passivated, and Al 2O 3 passivated configurations. The fabrication procedure is described and data pertaining to forward and reverse characteristics, yield and storage characteristics are presented. The Schottky barrier height is characterized by four independent measurements with excellent agreement between the various measurements. The barrier height is in the 0·710–0·760 V range and the typical ideality factor is ≤1·05. The devices exhibit ideal Schottky barrier behavior at least over the −50−100°C temperature range. The current gain of Schottky barriers with different Al layer thicknesses is measured under static electron bombardment over the 1–30 keV energy range. From these measurements, the average energy required to create a hole-electron pair is determined to be 3·44±0·2 eV. Using the gain-energy characteristic, it is possible to identify an optimum accelerating potential for each target. This optimum accelerating potential is in good agreement with that obtained theoretically from consideration of target losses. No junction instability is observed due to electron irradiation for beam current densities up to 0·314 A/cm 2 and target current densities exceeding 1000 A/cm 2. Further, no significant device degradation is observed for target dissipated power densities exceeding 50 kW/cm 2. Under pulse mode dynamic testing, output pulses of 13·1 A with a measured risetime of 0·72 nsec into the 10 Ω optimum load are obtained. When the output risetime is corrected for beam resetime (∼0·60 nsec), an output/risetime of 13·1 A/0·40 nsec is obtained. This is within a factor of 2 of the theoretical output capability of an optimized target; the difference is due to the capacitance of the guard-ring. The amplifier pulse mode efficiency is 85 per cent. The low pass bandwidth is 875 MHz, and the Pf 2 figure is 82 W-GHz 2. In addition, small-signal transconductance and power gains of 4·35 ℧ and 40 dB, respectively, are achieved. No output pulse distortion or pulse height deterioration is noted for pulse widths up to 130 nsec having 13·0 A amplitude under prolonged bombardment of our devices. This indicates that if any insulator charging is occurring, it does not result in any deleterious effects on the target performance.

Technologie des circuits hybrides: Réalisation d'un amplificateur rapide 1 ns

A fast rise-time amplifier (1 ns) has been made using hybrid microcircuit technology. This is a single polarity pulse amplifier with a 20 dB voltage gain. We used thin film technology on ceramic substrates and an electron-beam gun for evaporating the tantalum and gold. An investigation of the amplifier has indicated that the characteristics of the hybrid microcircuit are better than those of the printed circuit version. The improvements are a shorter output rise-time and an aperiodic response.

A large fast water Cherenkov counter

A description is given of a large-volume Cherenkov counter with diffuse reflecting inside walls. Particular attention is given to the timing properties and it is shown that the chosen combination of the reflectivity of the walls and the number of photomultiplier tubes gives an output rise time of about 12 ns. The performance of the counter in two experiments is discussed.

300 megacycle logic with M.E.C.L. III

Two high speed logic circuits developed for a high energy physics experiment have easily met or surpassed the performance of the best available commercial logic at a fraction of commercial costs. A four fold coincidence-latch circuit and an eight fold fanout circuit built with Motorola M.E.C.L. III integrated circuits demonstrate that discrete component logic even at the highest attainable speeds is fast approaching obsolescence. The output rise time of the coincidence circuit is 0.8 ns with a pulse pair resolution of less than 3 1 3 ns . The output rise time of the fanout is 1.0 ns with a pulse pair resolution of 4 ns. The circuits are completely dc coupled and N.I.M. compatible. Development work was completed on these circuits by July 1970. This paper is a condensation of a University of Maryland technical report on the same subject (# 71-102).

An Experimental Comparison Between Direct and Indirect PAM by a High-Efficiency Microwave Frequency Multiplier with Varactor Diodes (Correspondence)

Two pulse amplitude modulation (PAM) methods by a high-efficiency frequency multiplier with varactor diodes are compared. Typical results achieved for an X-band to Q-band tripler prove that the direct PAM is better than the indirect one under the same conditions. The former acts as a pulse shaper (PS), and has an output rise time smaller than the rise time of the output voltage of the modulator chain.

Simple technique for measuring pulse shapes from nuclear detectors

A simple technique is described for measuring and recording pulse shapes and risetimes from nuclear detectors. The system uses a sampling scope as the basic component. Three dimensional data from the scope can be photographed and/or digitized and stored in a 2-parameter multichannel analyzer. The technique is applicable to scintillation detectors. solid state detectors, proportional counters, or any device with an output risetime from a few nsec to several μsec. The system can be assembled from general purpose instruments commonly found in most laboratories. Pulse shape distributions from several types of detectors are presented.