Output Phase Noise Research Articles

RF Frequency Synthesizer Based on Self-Mode-Locked Multimode Lasers

Low-noise local oscillators are very important in modern communication systems. To realize a stable solution with a limited size, symmetric multimode multi-section semiconductor laser pairs are reported in this article for building a chip-level RF synthesizer. The symmetric laser structure utilizes a shared distributed Bragg reflector (DBR) and counterpropagating laser output with the help of an external feedback circuit to achieve self-mode-locking. The achieved phase noise performance is −92 dBc/Hz at a 10 kHz offset frequency for intermodal operation at 26.4 GHz using 5 locked modes, which is a 57 dB improvement compared to the free-running case. Moreover, an RF synthesizer covering frequencies of 11–13 GHz is realized based on the achieved mode-locked system using current tuning. The related phase noise of the laser pair beat-note output is −100 dBc/Hz at a 10 kHz offset of carrier frequencies of 11–13 GHz, which is 58 dB better than the phase noise of the beat-note output without mode-locking over 11–13 GHz.

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz–6.1 GHz Applications in 0.18 μm CMOS

The differential ring voltage controlled oscillator (VCO) is one of the critical devices in wireless communication system having excellent stability, controllability and noise rejection ability. A novel design of delay cell is proposed for the four staged CMOS differential ring VCO with high output frequency, low power consumption and low phase noise. The differential ring VCO utilizes multiloop dual delay path topology to acquire both high output frequency and low phase noise. Results have been achieved in TSMC 0.18-[Formula: see text]m CMOS process with a supply voltage ([Formula: see text]) 1.8[Formula: see text]V. The proposed design achieves an output frequency range of 4.029[Formula: see text]GHz to 6.122[Formula: see text]GHz and power of 4.475[Formula: see text]mW is consumed with control voltage variation from 1[Formula: see text]V to 2[Formula: see text]V. The proposed VCO exhibits [Formula: see text]89.7[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset frequency and the corresponding figure of merit (FoM) is [Formula: see text]155.9[Formula: see text]dBc/Hz. The design of differential ring VCO with novel delay stage has improved performance in terms of power consumption, output oscillation frequency and phase noise.

Cascaded injection of semiconductor lasers in period-one oscillations for millimeter-wave generation.

Period-one (P1) oscillations in semiconductor lasers are applicable in photonic millimeter-wave (mm-wave) generation. P1 oscillation can be invoked by optically injecting a laser, where the phase noise can be suppressed by modulation. To increase the frequency range of mm-wave generation, cascaded injection is investigated for enhancing the P1 oscillation harmonics. Relative to the optical frequency of the injection from a master laser, P1 oscillation at frequency f0 is induced in a primary slave laser which, in turn, injects a secondary slave laser for enhancing the harmonic at 2f0. Experimentally, photonic mm-wave generation at 2f0=72 GHz is demonstrated using P1 oscillations at f0=36 GHz. Subharmonic locking by modulation at f0/4=9 GHz can suppress the output phase noise to -87 dBc/Hz at 10kHz offset. The mm-wave power can be strengthened by the coherent addition from the master laser. The mm-wave frequency can be tuned by varying the operating conditions of the lasers. Extension to higher frequencies is possible using the approach of cascaded injection.

Frequency domain signal and noise analysis of optoelectronic oscillators under the effects of modulator frequency chirping and fiber dispersion

The effects of the Mach–Zehnder modulator-induced frequency chirping and optical fiber dispersion on the signal transmission in a microwave photonic link (MWPL) have already been investigated. Here, a more general signal/noise transmission model for MWPLs is introduced. Then a new frequency domain approach utilizing the mentioned model is proposed for analyzing the combined effects of fiber delay line dispersion and modulator frequency chirping on the signal and noise performance of a single-loop optoelectronic oscillator (OEO). It is shown that the dispersion of the fiber delay line and the modulator chirp can largely affect the open-loop gain of the OEO. Consequently they affect the oscillation amplitude such that neglecting them may result in inappropriate adjustment of the small signal gain. Although dispersion of the fiber delay line is the main mechanism through which the laser frequency noise (LFN) contributes to the output phase noise, it is shown that dispersion can reduce the output phase noise due to the noise of the RF amplifier (RFA) up to about 30 dB. In addition, it is shown that a negative chirp results in about 0.5 dB extra reduction of the contribution of the RFA noise in the output phase noise, but for positive chirp values it results in about 15 dB deterioration of noise compared to the dispersion-only case. The chirp effect is negligible for the LFN-induced phase noise. The validity of the new approach is verified by comparing its results with those from other simulation approaches in the literature.

Low phase‐noise high output power 176‐GHz voltage‐controlled oscillator in a 130‐nm BiCMOS technology

In this study, the authors present the design and measurement results of a voltage-controlled oscillator (VCO) that is based on a Colpitts core topology and a cascade output buffer. The circuit has a centre frequency of 176 GHz and is implemented in a 130 nm SiGe BiCMOS technology provided by IHP foundry. The VCO is a differential fundamental wave tunable oscillator that makes use of a transistor-based LC-resonator. On-wafer measurements show a tuning range of about 5% from 171 to 179.5 GHz. The circuit achieves a maximum output power of 7.3 dBm when biased at 1.6 V and 6.5 dBm if biased at 1.4 V, both with an efficiency of ∼ 6.6%. DC power consumption is 82 and 52 mW, respectively. The measured phase-noise of the VCO is − 110 dBc/Hz at 10 MHz offset. The VCO demonstrates state-of-the-art performance at these frequencies with very good performance in term of output power, efficiency linearity, phase noise and compactness; in addition, thanks to the proposed architecture it shows high integrability at the system level.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Wandering Spurs in MASH 1-1 Delta-Sigma Modulators

Wandering spurs are a little-studied phenomenon seen in MASH and SQ-digital delta–sigma modulators. They take the form of frequency-modulated spurs which periodically appear in-band. Since modulators are often employed as divide ratio controllers in fractional- ${N}$ phase lock loops, these spurs can feed into the output phase noise spectrum. In this paper, we explain the mechanism which creates the wandering spurs and offer a prediction for the behavior of these spurs in the MASH 1-1 modulator. Simulation results are presented which confirm our theoretical predictions.

A CMOS based low power digitally controlled oscillator design with MOS varactor

With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of VDD from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise.

1/f3 (Close-in) Phase Noise Reduction by Tail Transistor Flicker Noise Suppression Technique

In this paper, a novel circuit method is proposed to reduce 1/f3 (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/f3 output phase noise is reduced by 5.7[Formula: see text]dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V supply and 3.6[Formula: see text]mW power consumption. Post-layout simulations predict a phase noise of [Formula: see text][Formula: see text]dBc/Hz for the proposed oscillator at 100[Formula: see text]KHz offset from 3.1[Formula: see text]GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6[Formula: see text]dBc/Hz at 100[Formula: see text]KHz and 1[Formula: see text]MHz offsets, respectively.

A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS

A 9-GHz sub-integer frequency synthesizer incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5 V, phase-switching-based programmable division for sub-integer frequency synthesis, and automatic calibration to ensure injection lock. The synthesizer consumes 3.5 mW of power at 9.12 GHz and 0.05 mm2 of area, while showing an output phase noise of −100 dBc/Hz at 1 MHz offset and RMS jitter of 325 fs; it achieves a net FOMA of −186.5 in a 45-nm SOI CMOS process.

A Push-push Dual-band Cross-coupled VCO in 90-nm CMOS Technology

This paper presents a VHF dual-band cross-coupled voltage VCO with push-push structure. This is achieved by using the push-push structure and the binary-weighted capacitor. The circuit has been implemented in TSMC 90nm CMOS process with a core area about 800μm ×600μm. The measured fundamental and push-push output phase noise at 10MHz is-108.57 dBc/Hz and-98.43 dBc/Hz, with the tuning range covers 26.38 GHz～28.15 GHz and 52.76 GHz～56.30 GHz.

Optical injection locking at sub nano-watt powers.

We demonstrate optical injection locking (OIL) at record low injection power of -65 dBm using EDFA-based pre-amplification and an electrical phase locked loop (PLL). Investigating the phase noise characteristics of OIL, we find that at low injection powers the slave laser linewidth and injection ratio strongly influence the phase noise of the locked slave output. By introducing an EDFA pre-amplifier, the minimum locking power for OIL is reduced. Moreover, using this pre-amplifier we find that there exists an optimum injection power into the slave where the output phase noise is minimized and is below the phase noise without EDFA. We evaluate an OIL-based pump recovery in a phase sensitive amplifier (PSA) receiver system aimed at free-space communications.

Design of low phase-noise oscillators based on microstrip triple-band bandpass filter using coupled lines resonator

This paper presents new low phase noise oscillators employing a triple-band bandpass filter as a frequency stabilization element into the feedback loop. In addition, using triple-band bandpass filter (TB-BPF); three oscillators can be easily achieved separately, only by changing the length of the transmission line in feedback loop. The oscillators are designed at the spectrum-based quality factor (Qs) peak frequencies of bandpass filter to achieve low phase noise performance. Also, the oscillation frequencies of the oscillators are designed at 3.4, 4.33 and 6.89 GHz, resulting in achieving the simulated phase noise of these oscillators are −166, −154 and −150 dBc/Hz at the 1-MHz offset frequency respectively. The oscillator with 3.4 GHz carrier frequency is fabricated and the measured results show the 10.7 dBm output power and phase noise is −163 dBc/Hz at 1-MHz frequency offset. The figure of merit of the fabricated oscillator at 1 MHz offset frequency is −218.9 dBc/Hz.

Low supply voltage and multiphase all‐digital crystal‐less clock generator

A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from - 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and - 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm 2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula> Frequency Synthesizers

Fractional- $N$ frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM). Because the MASH DDSM suffers from performance degradation in the presence of nonlinearities, Galton et al. introduced a new divider controller architecture called the Successive reQuantizer (SQ). The SQ is designed to eliminate spurious tones caused by polynomial nonlinearities of a given order. A drawback of the SQ is that its hardware consumption is significantly higher than that of a MASH DDSM. A nested MASH-SQ hybrid has been introduced to achieve similar spectral performance to the SQ but with reduced hardware cost. In this paper, we present a design method for a nested MASH-SQ hybrid divider controller for fractional- $N$ frequency synthesizers.

A low phase noise super–harmonic coupling quadrature VCO using an additional double frequency oscillator

In this paper, using an additional oscillator that operates at twice the main output frequency, super–harmonic coupling is created between two LC cross–coupled oscillators. The additional oscillator output signals are injected into the two main oscillators in a special way, such that in addition to forcing those oscillators to work in quadrature mode, a tail current shaping technique is performed on them, through the same circuit path. As a result, the main oscillators output phase noise is reduced. The second harmonic signals with the help of two additional NMOS transistors shape the gate voltages and consequently the drain current of the tail transistors. The quadrature mode operation of the proposed circuit is mathematically proved and the intrinsic tail current shaping behavior of it is analyzed. The proposed QVCO is designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V and a total power consumption of 4.4 mW at 2 GHz center frequency with 5.5% tuning rage. Simulation results confirm the proposed quadrature mode operation. It also shows the phase noise of −128.1 dBc/Hz for the proposed QVCO at 1 MHz offset and 1.92 GHz carrier, which is 9.3 dB better than that of the conventional Parallel (P)–QVCO. The maximum phase error for 0.5% I and Q tank capacitor mismatch is 1.47°.

Design of CMOS-based low-power high-frequency differential ring VCO

ABSTRACTAn improved design of four-stage CMOS differential ring voltage-controlled oscillator (VCO) with high-output frequency, low phase noise, and low power consumption is proposed in this paper. A new differential delay cell has been used for differential ring VCO which utilises dual-delay-path topology to attain both high-output frequency and low phase noise. The simulation results have been obtained in TSMC 0.18-µm CMOS process with a supply voltage (Vdd) 1.8 V. The proposed design of VCO exhibits an output oscillation frequency range from 1.619 to 3.712 GHz. The power consumption for this frequency range varies from 4.628 to 10.545 mW with control voltage variation from 0.1 to 1.0 V. The proposed design occupies compact layout area of 0.207 mm2 and achieves – 89 dBc/Hz phase noise at 1 MHz offset from 3.712-GHz carrier frequency. Improved performance for this design has been achieved in terms of output oscillation frequency, phase noise, and power consumption.

Demonstration of a highly stable 10 GHz optical frequency comb with low timing jitter from a SCOWA-based harmonically mode-locked nested cavity laser.

An optical frequency comb with mode spacing of 10GHz operating in the c-band is produced from a harmonically mode-locked laser using a slab-coupled optical waveguide amplifier device with a fiber-coupled external cavity. An intracavity Fabry-Perot etalon serves as a high finesse optical filter for supermode suppression and as the reference for cavity length stabilization using a multi-combline Pound-Drever-Hall setup. The Allan deviation of a single optical combline near 193.4THz is measured via a heterodyne beat with a cavity stabilized cw laser and reaches a minimum fractional frequency deviation of 3×10-13 at τ=30 ms. In addition, the phase noise of the photodetected pulsed output of the laser shows a timing jitter of <23 fs integrated from 1Hz to the Nyquist frequency.

Design of Negative Resistance Oscillator with Rocord Low Phase Noise

The aim of this paper is to use a new design of a negative resistance microwave oscillator in order to fabricate oscillator with very good performance in terms of output power, efficiency, stability and phase noise. In this study the new concept of oscillator using distributed resonator and micro-strip circuit elements improve performances of our structure. A micro-strip microwave oscillator with low phase noise based on an NPN silicon planar epitaxial transistor has been designed, fabricated, and characterized. In this design, each step has been conducted by using Advanced Design System (ADS) and following a theoretical study which enable to optimize the different performances of the whole circuit. The oscillator produce a sinusoidal signal with spectrum power of 12.25 dBm at 2.45 GHz into 50 Ω load when polarized at Vcc=15V with DC to RF efficiency of 16. The obtained phase noise of -120 dBc/Hz at 100 Hz offset is the result of the use of high Q factor resonator and the depth study of the parameters of the oscillator. Simulation and measurement results are in good agreement.

Design of Linear Low-Power Voltage-Controlled Oscillator with I-MOS Varactor and Back-Gate Tuning

This paper reports a new design of CMOS voltage-controlled oscillator (VCO) using three-transistor XOR gate and inversion mode MOSFET varactor tuning concept. Output frequency in the VCO has been varied by varying the output node capacitance with the use of inversion mode MOSFET tuning and back-gate tuning. Further, variation in the output frequency has been obtained with the power supply tuning for different value of back-gate voltages. Inversion mode MOSFET tuning has been achieved by varying the source/drain voltage from 0.6 to 2.2 V which provides the frequency variation from 1.630 to 1.232 GHz with power consumption of 296.393 $$\upmu \hbox {W}$$ for inversion mode MOS varactor width of 5 $$\upmu \hbox {m}$$ . Results have also been obtained with inversion mode MOS varactor widths of 8 and 10 $$\upmu \hbox {m}$$ . Output frequency, power consumption and phase noise results have also been reported for the different values of back-gate and power supply voltages. A tuning range of 27.8, 32.7 and 34.3% has been achieved with the source/drain tuning for inversion mode MOS varactor width of 5, 8 and 10 $$\upmu \hbox {m}$$ , respectively. Moreover in power supply tuning the tuning range of approximately 134% has been obtained for different widths of inversion mode MOS varactor. VCO is showing the phase noise of $$-\,97.216$$ dBc/Hz with an offset of 1 MHz from the carrier. Proposed VCO shows a linear tuning, low-power consumption and good phase noise performance.