Design of CMOS-based low-power high-frequency differential ring VCO

Abstract

ABSTRACTAn improved design of four-stage CMOS differential ring voltage-controlled oscillator (VCO) with high-output frequency, low phase noise, and low power consumption is proposed in this paper. A new differential delay cell has been used for differential ring VCO which utilises dual-delay-path topology to attain both high-output frequency and low phase noise. The simulation results have been obtained in TSMC 0.18-µm CMOS process with a supply voltage (Vdd) 1.8 V. The proposed design of VCO exhibits an output oscillation frequency range from 1.619 to 3.712 GHz. The power consumption for this frequency range varies from 4.628 to 10.545 mW with control voltage variation from 0.1 to 1.0 V. The proposed design occupies compact layout area of 0.207 mm2 and achieves – 89 dBc/Hz phase noise at 1 MHz offset from 3.712-GHz carrier frequency. Improved performance for this design has been achieved in terms of output oscillation frequency, phase noise, and power consumption.