Output Offset Voltage Research Articles

A −184 dB PSRR and 2.47 [formula omitted] noise self biased bandgap reference based on FVF structure

A high power supply rejection ratio (PSRR), low noise and low-power self-biased bandgap voltage reference (BGR) is presented in this paper. In response to the trade-off between power consumption and output noise, a feedback depth enhancement technique is proposed for mitigating the effect of the resistor on output noise and offset voltage. The PSRR is enhanced by a novel self regulating technology based on an improved flipped voltage follower (FVF). The designed BGR was verified under post-simulation for various process corners, voltages and temperatures (PVT). It was using 0.18μm BiCMOS process, occupying an active area of 0.016 mm2. The BGR operates normally at 3.0 V – 3.6 V with a quiescent current of 3.6 μA. The best untrimmed TC is 22.04 ppm/∘C and the rms noise is only 2.47 μVrms from 0.1 Hz to 10 Hz. The PSRR is −184 dB@1 Hz and −50 dB@1 MHz when VIN = 3.0 V.

Wattmeter based on tunnel-effect magnetoresistance sensor.

This work shows how the tunnel-effect based magnetoresistance (TMR) technology can be used as a competitive sensing method in electrical current and power processors. The sensor is arranged in a Wheatstone bridge topology, and each magnetoresistance was composed of a series connection of 360 magnetic tunnel junction elements with the following structure (thickness in nm): 100 SiO2/5 Ta/15 Ru/5 Ta/15 Ru/5 Ta/5 Ru/20 IrMn/2 CoFe30/0.85 Ru/2.6 CoFe40B20/1.2 MgO/2 CoFe40B20/0.21 Ta/4 NiFe/0.20 Ru/6 IrMn/2 Ru/5 Ta/10 Ru. First, the electrical and thermal characteristics of the sensor were evaluated by analyzing its response to DC current sweeps at various temperatures, controlled using a climatic chamber. Nominal values of current sensitivity S (0.324 mV/A), bridge output offset voltage Vo,s,o (-37.1 mV), bridge input resistance Rinp,bridge (0.958 kΩ), and their thermal behavior were obtained (0.0036 mV/A°C, 0.079 mV/°C, and -0.31 Ω/°C). Second, an instrumentation system is introduced to characterize the sensor, measuring its sensitivity to AC line currents from the mains up to 10Arms. Finally, an electronic wattmeter was developed showing the relevant quantities of its design. The circuit is able to interface a TMR Wheatstone bridge to an analog processor. Power and current measurements were obtained from a 150Vrms AC mains 1.5 kW load with resistive and capacitive components, achieving less than 1% deviation over the expected values. The circuit shown can be used to interface these signals to more complex smart digital engines with active or reactive energy processing capabilities, while providing inherent high voltage isolation, thanks to its TMR measurement technology.

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

Lossy Integrator Readout Circuit With Active Bias Point

The charge-generating sensors are widely used in many applications in consumer, automotive and medical electronics. They generate a charge proportional to the applied input quantity: pressure, temperature, acceleration, strain, light, etc. Usually, charge amplifiers are used to register such signals. The charge amplifier is an integrator that integrates the input current over time. In continuous-time signal processing, a parallel resistor is used to dissipate the energy stored on the integration capacitor, and such self-zeroed integrator circuits are known as lossy integrators. To achieve low-frequency operation, when a capacitor is in the picofarad range, a very high-ohmic resistor, in the range of gigaohms, must be used. Such a high-ohmic resistor increases the output offset voltage to an unacceptable level. To overcome the output offset problems, a composite charge amplifier has been recently introduced. This paper presents an innovative lossy integrator readout circuit which contains only one opamp in the feedback. The circuit can be easily adapted to the needed gain and cut-off frequency. Its operation is validated by experimental results. The sufficiently low high-pass cut-off frequency allows the circuit to be used for biosignal amplification. Heart and respiration rates can be easily recorded with piezoelectric sensors attached to the wrist or lung wall. The presented circuit can benefit many applications where charge-to-voltage conversion is needed.

Modeling and Simulation of Monolithic Single-Supply Power Operational Amplifiers

In this paper a simple PSpice (Personal Simulation Program with Integrated Circuit Emphasis) macro-model was developed, and verified for monolithic power operational amplifiers operated with a single-supply voltage. The proposed macro-model is developed using simplification and build-up techniques for macro-modeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macro-model also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model is implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit is built using standard PSpice components and analog behavioral modeling blocks. The accuracy of the model is verified by extracting the model parameters for single-supply power operational amplifier TDA2005 from ST Microelectronics as example. The effectiveness of the model is validated by comparing the simulation results of the electrical parameters with the corresponding measured values obtained by experimental testing of sample circuits. The comparative analysis shows that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.

A Fast-Response RBAOT-Controlled Buck Converter With Pseudofixed Switching Frequency and Enhanced Output Accuracy

A ripple-based constant on-time (RBCOT) control scheme is excellent in achieving fast transient response during the load current step. However, it suffers from severe electromagnetic interference (EMI) noise and inherent output voltage offset problem. A monolithic ripple-based adaptive on-time (RBAOT)-controlled buck converter is presented to overcome both drawbacks while retaining the advantage of RBCOT. The on-time is adjusted adaptively by detecting the switching node voltage, and thereby ensuring a pseudofixed switching frequency in a steady state, regardless of the input, output voltage, and load current conditions. A correction voltage generated by a coefficient in a virtual inductor current (VIC) circuit is introduced to counteract the offset voltage and enhance the output accuracy. The proposed scheme is simple to implement and suitable for high-conversion ratio applications. Experimental results show that the switching frequency is centered at 1 MHz with less than 6% variation for an output of 5 V and inputs ranging from 8 to 18 V. The output offset voltage is reduced from 16 to 1 mV for an 18 to 1.05-V conversion. For a load current step of 1 A, the output can be settled within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6~\mu \text{s}$ </tex-math></inline-formula> and the undershoot and overshoot voltages are controlled to be within 20 mV.

Compact CMOS Miller OpAmp With High EMI-Immunity

In this work, a CMOS Miller Operational Amplifier (OpAmp) with high immunity to electromagnetic interference (EMI) is proposed. The proposed OpAmp has unique features, such as compact power and low output offset voltage, when compared to the classical Miller OpAmp and the robust Miller OpAmp reported in the literature. The proposed compact Miller OpAmp has a reduced area, when compared to the robust Miller OpAmp. The output offset current modeling equations are derived for the proposed compact Miller OpAmp including the body effect and channel length modulation. The results are validated with simulations in the presence of a test EMI signal of 1 Vpp in 1.8 V, 0.18 $\mu$ m CMOS technology. The power consumption of the proposed compact Miller OpAmp with source degeneration resistance $R_S$ is 8% less and the area is 5.6% less than the robust Miller OpAmp with source degeneration resistance $R_S$ . The performance result shows that the maximum EMI-induced input offset voltage for the proposed compact Miller OpAmp with source degeneration resistance $R_S$ is 4.6 mV over a wide frequency range from 1 MHz to 1 GHz, which is lower when compared to the classical Miller OpAmp and the robust Miller OpAmp with source degeneration resistance $R_S$ .

A Novel Low Output Offset Voltage Charge Amplifier for Piezoelectric Sensors

The charge amplifier is an important building block in various electronic circuits. In this paper a new charge amplifier for piezoelectric sensors is introduced. The advantages of the new proposed charge amplifier becomes obvious in the quasi-static applications. In some quasi-static applications the traditional charge amplifiers uses an extremely large feedback resistor (in the range of GQ) whereas the proposed charge amplifier no longer requires such extremely large resistors. Moreover the proposed circuit reduces the output offset voltage significantly in comparison with conventional charge amplifier. The proposed circuit can be also implemented by using general purpose JFET operational amplifiers instead of using electrometer operational amplifiers therefore the cost of implementation will be reduced significantly in comparison with conventional charge amplifier. The proposed charge amplifier was assembled by using general purpose JFET Op-Amp to capture and amplify the output voltage of the piezoelectric vibration sensor Minisense100. In this experiment the low-cutoff frequency and the gain of the proposed charge amplifier were set equal to 0.2Hz and 20.5 dB respectively. The output offset voltage of the circuit was measured equal to 210 μV .The measurement of very small vibration (±0.015g) showed a relative error equal to 2.1% with respect to the value which is obtained by using vibration meter as reference.

A High Speed Latched Circuit for Flash ADC

Practically all electronic systems are realized using integrated circuit(IC) chips. The IC design requires digital signals, but however the physical signals available routinely are either continuous time varying signals or corrupted discrete voltages. These continuous time varying input signals are converted to full voltage swing digital signals by means of a comparator circuit. The comparators use regenerative feedback to transform the output to a full scale digital signal. The core specifications considered in this comparator implementation are power dissipation (PD), propagation delay (tP), output offset voltage and slew rate. The circuit is simulated in CMOS 180nm technology using Tanner EDA tool. The high speed latched comparator circuit is powered with a 1.8V DC power supply and the obtained results show that it operates at 1.67GHz, slew rate is 126 V/μS and the dynamic power dissipation is found to be 0.328mW.

An energy-efficient, 6 GS/s dynamic comparator in 90 nm CMOS technology

In this paper, a two-stage dynamic comparator circuit is proposed, which considerably reduces the power consumption as well as the power-delay product parameter, while improves the speed. Furthermore, the performance of the pre-amplifier stage in the proposed design is improved which properly reduces the kick-back noise as well as the power consumption. The proposed circuit operates at 1 V supply at the clock frequency of 6 GHz (high-speed scenario), which results in the static and dynamic power consumption of 112.77 nW and 848 μW, respectively. Moreover, the delay of the circuit is 36.6 ps, while the output offset voltage is only 8 mV, with the kick-back noise of 48 mV. On the other hand, the circuit can operate at 1 V supply and frequency of 500 MHz (low-power scenario), which results in the reduced static and dynamic power consumption of 112.77 nW and 188.9 μW, respectively while the offset of the circuit can be reduced to only 1 mv at the delay of 46.4 ps and kick-back noise of 39.75 mV.

An Analytical Theory of Piezoresistive Effects in Hall Plates with Large Contacts

Four-terminal transducers can be used to measure the magnetic field via the Hall effect or the mechanical stress via the piezoresistance effect. Both effects are described by an anisotropic conductivity tensor with small offdiagonal elements. This has led other authors to the conclusion that there is some kind of analogy. In both cases the output voltage depends on the geometry of the device and the size of the contacts. For Hall plates this influence is accounted for by the Hall-geometry factor. The alleged analogy proposes that the Hall-geometry factor also applies to four-terminal stress transducers. This paper shows that the analogy holds only for a limited class of devices. Moreover, it is shown that devices of different geometries may have identical magnetic field sensitivity but different mechanical stress sensitivities. Thus, shape optimization makes sense for mechanical stress sensors. In extreme cases the output voltages of vertical Hall-effect devices may have notable magnetic field sensitivity but zero mechanical stress sensitivity. As byproduct, exact analytical formulae for the equivalent resistor circuit of rectangular and circular devices with two perpendicular mirror symmetries are given. They allow for an accurate description of how mechanical stress and deformation affect the output offset voltage and the magnetic sensitivity of Hall-effect devices.

A ROIC for Diode Uncooled IRFPA With Hybrid Non-Uniformity Compensation Technique

A CMOS readout integrated circuit with non-uniformity calibration for diode uncooled infrared focal plane array (IRFPA) is presented in this paper. Pixel signals are sampled and held by a capacitor, eliminating the extra current of the reference pixel. We propose a new transconductance amplifier with offset cancellation structure, utilizing output offset voltage storage. A novel 8-b current splitting DAC array is proposed in this paper. With the help of an off-chip ADC, the bias current of each pixel can be adjusted by DAC array, calibrating the non-uniformity of the IRFPA. The proposed circuit with 32 readout channels is fabricated using a 0.35- $\mu \text{m}$ standard CMOS process. The measured results show that the average output offset voltages are 600 and 40 mV before and after calibration, respectively. The non-uniformity calibration technique has been proven very effective with 95% offset decrement, and this paper is especially suitable for large-scale image sensor.

Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation

This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and channel length modulation. The circuit has been fabricated using 0.18 $\mu \text{m}$ mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB**Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Key Laboratory of Precision Navigation Technology and Application Foundation (No. DH201501).

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

Total ionizing dose (TID) evaluation of magnetic tunnel junction (MTJ) current sensors

The paper shows an experimental study to know the behaviour of tunnel magnetoresistive effect-based current sensors configured in a Wheatstone bridge in response to irradiation. In particular the sensitivity, hysteresis, output offset voltage and input resistance are discussed when the sensors are submitted to a total irradiation dose of 43krad with 36krad/h dose rate. The same electrical parameters were studied subsequently once the irradiated sensors were submitted to an 80°C annealing process. The studied TMR sensors are applied in a switched-mode power converter for space application.

Digital Offset Trimming Techniques for CMOS MEMS Accelerometers

This paper presents a digital trimming technique for canceling the output offsets caused by sensor mismatches in an accelerometer design. The offset cancellation techniques provide fine trimming steps with higher chip area efficiency compared with that of conventional capacitor array compensation approaches. The accelerometer, fabricated in a 0.18- μm complementary metal-oxide-semiconductor micro-electro-mechanical-system process, containing the micro-mechanical structure and readout circuits, occupies only a 0.64 × 0.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. The chip draws 0.4 mA from a 1.8-V supply. The measured sensitivity is 195 mV/g and the nonlinearity is 0.78% within the ±12 g sensing range. The output noise floor is 150 μg/√{Hz}, corresponding to a 1-g 100-Hz sinusoidal acceleration. The output offset voltage can be trimmed from several tens to several hundreds of millivolts down to several millivolts.

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm2, and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G−1with a standard deviation of 2.5 mV G−1. The measured output noise floor is 354 µG Hz−1/2, corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C−1 below 85 °C.

Capacitor-based isolation amplifiers for harsh radiation environments

Commercial-off-the-shelf (COTS) capacitor-based isolation amplifiers were irradiated at the Portuguese Research Reactor (PRR) in order to determine its tolerance to the displacement damage and total ionising dose (TID). The set of experimental data shows that some of these devices are suitable for zones inside future nuclear facilities where the expected total radiation damage would be below 2.2 × 10 13 1 ‐ MeV neutron / cm 2 and 230 Gy (Si). However, some drawbacks must be taken into account by the electronic designers such as the increase of the output offset voltage and the slight modification of the transmission gain.

An offset-insensitive switched-capacitor bandgap reference with continuous output

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/°C and the power supply rejection ratio of output voltage without any filtering capacitor is −40 dB and −33 dB at 100 Hz and 10 MHz, respectively.

Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package

A new hybrid modeling method is proposed for the chip-package co-modeling and co-analysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 mum. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package co-modeling and simulation of the system-in-package designs.