Output Impedance Matching Research Articles

Compact Wideband Antiparallel Diode Frequency Triplers Utilizing Planar Transitions

Two designs of frequency triplers, which use planar transitions as baluns and an antiparallel diode pair to achieve wide bandwidth, are presented. The ultrawideband transitions are utilized for input and output impedance matching of the frequency triplers. The design process and operation principles are described in this paper. The implemented frequency triplers exhibit flat response over wide frequency range of 3 to 9 GHz. The proposed Type A frequency tripler shows conversion loss of ~18 dB with above 30 dB even harmonics suppression. With Type B frequency tripler, conversion loss of ~17 dB and above 25 dB even harmonic suppression are achieved.

A 60 GHz power amplifier with Psat of 13.1 dBm, PAE of 11 % and excellent matching in 90 nm CMOS for 60 GHz short-range communication systems

A 60 GHz power amplifier (PA) for direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with inductive interconnection and load, followed by a common-source gain stage and a common-source output stage with source-degeneration. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wideband input and output impedance matching to 100 Ω. This in turn results in further PSAT and PAE enhancement. The PA consumes 128 mW and achieves power gain (S21) of 11.5 ± 0.4 dB, input-port input reflection coefficient (S11) of ?15.7 to ?17.9 dB, and output-port input reflection coefficient (S22) of ?15.5 to ?30.8 dB for frequencies of 57---64 GHz. In addition, the PA achieves output 1-dB compression point (OP1dB) of 7.5 dBm, PSAT of 13.1 dBm and maximum PAE of 11 % at 60 GHz, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60-GHz short-range communication system applications.

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 $$\upmu \hbox {m}$$ μ m CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5---3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18 $$\upmu \hbox {m}$$μm technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than $$-$$-11.6, output return loss of $$-$$-19.2 to $$-$$-19 and reverse isolation of $$-$$-38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.

Wideband Four-Way Out-of-Phase Slotline Power Dividers

Two new wideband four-way out-of-phase slotline power dividers are proposed in this paper. The half-wavelength slotlines are employed to construct the presented compact power dividers. Based on the proposed power-dividing circuit, a four-way power divider is implemented with compact size and simple structure. To obtain high isolation among the four output ports and good output impedance matching, another four-way out-of-phase slotline power divider with improved isolation performance is designed by introducing an air-bridge resistor and two slotlines with isolation resistors. The simulated and measured results of the proposed power dividers demonstrate reasonable performance of impedance matching, insertion loss, amplitude balancing, and isolation among the output ports.

A high‐performance low‐noise amplifier for 71–76, 76–77, and 77–81 GHz communication systems in 90‐NM CMOS

ABSTRACTA low power and wideband three‐stage millimeter‐wave low‐noise amplifier (LNA) for 71–76 GHz high‐speed point‐to‐point wireless link, and 76–77 GHz long‐range and 77–81 GHz short‐range automotive radars using standard 90‐nm CMOS technology is reported. T‐match technique is utilized to achieve simultaneously wideband input and output impedance matching, wideband power gain (S21) and wideband noise figure (NF) at W‐band. The LNA consumes 21.1 mW, achieving S11 better than −10 dB for frequencies 62.3–82.4 GHz, S22 better than −10 dB for frequencies 62.8–84.6 GHz, S12 better than −29 dB for frequencies 72–84 GHz, and group delay variation smaller than ±6.5 ps for frequencies 70–90 GHz. Additionally, high and flat S21 of 13.1 ± 1.5 dB is achieved for frequencies 72–84 GHz, which means the corresponding 3‐dB bandwidth is 12 GHz. Furthermore, the LNA achieves minimum NF of 6.2 dB at 78 GHz and NF of 6.8 ± 0.6 dB for frequencies 75–82 GHz, one of the best NF results ever reported for a W‐band CMOS LNA. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1673–1680, 2014

Low‐power 77–81 GHz CMOS LNA with excellent matching for automotive radars

A low-power and wideband three-stage 77–81 GHz low-noise amplifier (LNA) using standard 90 nm CMOS technology is reported. The T-match technique is utilised to achieve simultaneously wideband input and output impedance matching, wideband power gain (S 21) and a wideband noise figure (NF). The LNA consumes 21.1 mW, achieving S 11 better than −10 dB for the frequencies 62.3–82.4 GHz, S 22 better than −10 dB for the frequencies 62.8–84.6 GHz, S 12 better than −29 dB for the frequencies 72–84 GHz and a group delay variation smaller than ±4 ps for the frequencies 77–81 GHz. In addition, high and flat S 21 of 13.1 ± 1.5 dB is achieved for the frequencies 72–84 GHz, which means the corresponding 3 dB bandwidth is 12 GHz. Furthermore, the LNA achieves a minimum NF of 6.2 dB at 78 GHz and a NF of 6.8 ± 0.6 dB for the frequencies 75–82 GHz, one of the best NF results ever reported for a CMOS LNA for 77–81 GHz automotive radar applications.

Multi-Port Driven Radiators

Integrated multi-port driven (MPD) radiator design is presented as an approach that takes advantage of the increased design space offered by using a hybrid design of an antenna with multiple ports and its driver circuitry integrated together on a single substrate. This reduces costly losses by eliminating independent elements for power combination, output impedance matching networks, and power transfer by engineering current patterns on a chip based on the desired far field pattern. The electromagnetic radiation produced by a circularly polarized MPD antenna is calculated analytically to provide design intuition, with supporting electromagnetic simulations. A single element 160 GHz MPD antenna and the supporting driver circuitry is designed and fabricated in a 0.13 μm SiGe BiCMOS process. A tuned 8 phase ring oscillator generates the signal with each phase feeding class A power amplifiers that drive the antenna. The radiator achieves 4.6 dBm single element effective isotropically radiated power (EIRP) and total radiated power of -2.0 dBm at 161 GHz while consuming 117.5 mA DC current from a 3.3 V source. Measurements of three frequency bands at 145, 154 and 161 GHz show greater than 0 dBm EIRP for each band, demonstrating the wide band nature of the antenna.

An Active Inductor Based Low Noise Amplifier for RF Receiver

Low Noise Amplifier (LNA) is a significant part in Radio Frequency (RF) receivers and plays a key role in the chip size and the implementation cost. An LNA for RF receivers utilizing the active inductor is presented. The proposed design is an alternative solution to overcome the usage of passive inductors to reduce the chip area. Besides, the active inductor reduces the parasitic capacitors affect at high frequencies. Designed in 0.18-μm CMOS process, the LNA achieves a voltage gain of 20dB, a minimum Noise Figure (NF) of 3.1 dB with low power consumption and good input and output impedance matching at 2.45 GHz. With 0.003 mm2 chip area, the proposed design is suitable for portable wireless communication devices. DOI: http://dx.doi.org/10.5755/j01.eee.19.5.2158

CMOS Ultra-Wideband Low Noise Amplifier Design

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

A 4.5 mW 3–5 GHz low‐noise amplifier in 0.25‐μm silicon‐on‐insulator CMOS process for power‐constraint application

AbstractA 1.5 V 4.5 mW 3–5 GHz low‐noise amplifier (LNA) suitable for power‐constraint application is implemented in a 0.25‐μm silicon‐on‐insulator CMOS process.The designed LNA with good input and output impedance matching exhibits gain of 10.3 dB and 2–2.9 dB noise figure within the 3–5 GHz band. Moreover, the −3 dB bandwidth of the presented LNA is insensitive to process corner variations. A third‐order input intercept point of −5 dBm is also achieved for the LNA at 3.6 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:89–93, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27262

A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1dB, gain of 18.9–20.2dB, gain flatness of ±0.65dB, input third order intercept point (IIP3) of −7dBm at 6GHz, exhibits less than 16ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18mW.

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S 21 (Gain) of 22 dB, S 11 of −18 dB, S 22 of −16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm2.

High gain/power quotient variable‐gain wideband low‐noise amplifier for capsule endoscopy application

AbstractAn implantable high gain/power quotient variable‐gain wideband low‐noise amplifier (LNA) suitable for capsule endoscopy application is implemented in a 0.25 μm silicon‐on‐insulator CMOS process. With a current‐reused topology and wideband matching network, the presented LNA exhibits peak gain of 13.8 dB, 2.3 dB noise figure, more than 1 GHz bandwidth and 5 dB gain tuning range with good input and output impedance matching. The LNA consumes only 1.8 mW DC power from a supply voltage of 1.5 V. An excellent average gain/power quotient of 6.8 dB/mW is achieved. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2563–2565, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27111

Complementary DAC topology for reduced output impedance dependency and improved dynamic performance

A complementary current-steering digital-to-analogue converter (DAC) topology is introduced which reduces the impact of the current source finite output impedance on the harmonic distortion. Using both a NMOS and a PMOS current source transistor, the linearity is determined by the output impedance matching of both current sources. Application of this technique reduces the required output impedance by five to 10 times compared to a regular DAC.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented. The transformer not only accomplishes output impedance matching, but also acts as a balun for converting differential signals to single-ended ones. Under a supply voltage of 3.3 V, the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%. The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB, respectively. The die size is 0.91 × 1.12 mm2.

Optimum Design of Asymmetrical Multisection Two-Way Power Dividers With Arbitrary Power Division and Impedance Matching

A general analysis and design procedure is developed for the asymmetrical multisection power divider with arbitrary power division ratio and arbitrary specifications of input and output impedance matching over any desired frequency bandwidth. The even- and odd-mode analysis, which was previously applied to the design of multisection Gysel power dividers, required that the unequal power division ratios be accompanied with appropriately proportional output impedances. This requirement is relaxed here. The equivalent circuits are first obtained for the divider and then their scattering parameters are determined. Some error functions are then constructed by the method of least squares. Their minimization determines the geometrical dimensions of the optimum divider. An approximate method based on the even and odd modes is developed for its initial design of the divider. Two examples of single- and double-section dividers are designed. Their frequency responses of isolation and transmission coefficients are obtained by the proposed method, HFSS software, fabrication, and measurement. They agree within the approximate assumptions. A two-section and two-way power divider is designed and fabricated by the proposed method for the case of unequal port impedances in the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$L$</tex></formula> -band. The measured isolation between the outputs is better than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-{\hbox {22 dB}}$</tex></formula> in 44% of the band.

Simple method for characterizing linear multi-port microstrip structures

A simple method for the full characterization of passive n-port microwave monolithic integrated circuit (MMIC) structures using standard two-port vector network analyzer (VNA) measurements is presented. Its main advantages are: it does not require to perform measurements from all the ports of the network, no special calibration procedure is needed, the auxiliary terminations required by the procedure can be integrated at the border of the structure under test with minimal area increase, and it can be easily implemented in commercial CAD software. The method was applied to a nine-port microstrip structure corresponding to the output power combiner and impedance matching network of an X-band MMIC high power amplifier (HPA). The full S-parameter matrix was derived from two-port measurements and compared to the circuit–as well as electromagnetic (EM)-based simulations of the structure.

Dual- and Triple-Band Wilkinson Power Dividers Based on Composite Right- and Left-Handed Transmission Lines

This paper presents dual- and triple-band equal-split Wilkinson power dividers (WPDs) based on composite right- and left-handed transmission lines. Good isolation between output ports and impedance matching at input ports are achieved simultaneously at all pass-band frequencies for both dual- and triple-band WPDs. The theoretical closed-form design equations are derived, and the design allows a wide range of flexibility for the allocations of the passbands. To verify the proposed design, two prototypes are fabricated and measurements show good agreement with simulated data. The first design is a triple-band WPD with passbands centered at 0.8, 1.3, and 1.85 GHz, and the second one is a dual-band WPD with passbands centered at 0.7 and 1.5 GHz. The triple-band divider has a length of 0.66 wavelengths in the substrate and is more compact comparing to traditional WPDs. The dual-band power divider is designed to have a wide fractional bandwidth with more than 20% at the lower passband and 41% at the upper passband. Measurements also show a good insertion loss at each input port, which is less than 3.6 dB at the center of each passband.

Tunable CMOS Power Amplifiers for Reconfigurable Transceivers

This paper presents three CMOS power amplifiers (PA) which realize wide-tunable output impedance matching. For realization of multi-standard and single-chip transceiver, the prototypes were fabricated by 0.18µm CMOS process. The proposed PAs can achieve a tunable impedance matching within a wide frequency range by utilizing a resistive feedback and parallel resonator with an inductor and capacitor array. Therefore, the proposed PA has a realization possibility of isolator-less PA which contributes to decrease die area including external component. In other words, the PAs have tunable impedance matching function at their output ends. With a 3.3-V supply, three power amplifiers can cover frequency ranges of 0.9-3.0GHz, 2.1-5.8GHz, and 5.7-9.7GHz, respectively. The PAs realize P1dB of 21dBm, Psat of 22dBm, and PAEpeak of larger than 23%. The proposed PAs present a potential to realize multi-band transceivers without isolators.