Output Impedance Matching Research Articles

Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler

This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm2 and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.

A 100–180-GHz Coaxial Frequency Tripler Based on Copper Additive Manufacturing

This article presents a wideband coaxial D-band frequency tripler fabricated by copper additive manufacturing (AM). The central part of the tripler consists of two waveguide–coaxial transitions, a coaxial low-pass filter, an antiparallel Schottky diode chip, and an output impedance matching network. Most constitutions, except for the diode chip, are monolithically fabricated in one piece. The diode chip with additional thermal paths is specially designed to obtain a good thermal performance and better power handling. To facilitate the measurement, a waveguide fixture is also designed to convert the ports to standard waveguide ports (WR-19 and WR-6.5). The measurements show that the maximum output power of the tripler is 9.44 mW with about 182 mW of input power at 147 GHz and its 3-dB bandwidth is 45.2% from 108 to 171 GHz. Additionally, the tripler delivers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 1.87 mW of output power and better than 10 dB of return loss over the 100–180-GHz range. To the best of authors’ knowledge, this is the first AM coaxial ultra-wideband frequency multiplier reported in the open literature.

Mutually coupled CG-CS current reuse low noise amplifier architecture for 4 – 14 GHz frequency

Abstract The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34.

A 26/38-GHz Dual-Band Filtering Balanced Power Amplifier MMIC for 5G Mobile Communications

This letter presents a 26/38-GHz dual-band filtering balanced power amplifier (PA) using 100-nm GaAs process. Dual-band branch-line couplers are proposed for the balanced PA, which also engage into the dual-band input–output impedance matching and provide out-of-band rejection simultaneously. The proposed PA achieves the saturation output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula> ) of 27.7/26.9 dBm, output 1-dB compression point (OP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) of 27.1/25.6 dBm, peak power-added efficiency (PAE) of 31.5%/22.8%, and small signal gain of 22.4/15.8 dB at 26/38 GHz. At frequencies of 12, 34, and 45 GHz, the small signal suppressions are 45, 54, and 40 dBc, respectively. In virtue of the high output power in 5G band n258/n260 and good out-of-band rejection, the proposed PA can be a potential candidate for 5G applications.

A room-temperature, low-impedance and high-IF-bandwidth terahertz heterodyne detector based on bowtie-antenna-coupled AlGaN/GaN HEMT

In this paper, a 330 GHz terahertz heterodyne detector based on bowtie-antenna-coupled AlGaN/GaN high-electron-mobility transistor (HEMT) is designed and demonstrated. The bowtie antenna and a silicon lens couple the terahertz wave into a transmission line, in which the HEMT's channel generates both self-mixing and heterodyne signals. Compared to field-effect detectors without front low-noise amplifiers and output impedance matching, this detector boosts the intermediate-frequency (IF) bandwidth to 2.9 GHz due to a low output impedance of 505 Ω while maintaining a comparable sensitivity. With further sensitivity enhancement, such detectors would be developed into room-temperature, high-sensitivity, and high-IF-bandwidth heterodyne arrays.

Design of high‐efficiency , multi‐octave hybrid continuous mode power amplifier with novel low‐pass filtering matching network

This paper presents a design method for a multi-octave, high-efficiency power amplifier (PA) with a novel low-pass filtering matching network. Both extended continuous Class-F and continuous Class-F−1 are engaged to expand the design space for the ultra-broad operating band. A wideband vertex coupled radial stubs (VCRS) low-pass filter alongside a transmission line network (TLN) is proposed as an output impedance matching network of the PA. The wide rejection band and sharp transition band of this filter make it suitable for harmonic tuning PAs. To verify the feasibility of the proposed structure, the PA is fabricated and its performance is measured. The fractional bandwidth of 155% across 150 to 1200 MHz with a drain efficiency of 61%–73% and output power of 38.9–39.5 dBm is achieved.

Design of a Source Degenerated Cascode Stage Low Noise Amplifier for 5G Applications

Low Noise Amplifier (LNA) is the most critical part of a receiver front end in terms of the receiver performance. The performance tradeoff among input matching, noise figure, gain, and linearity are analyzed in detail. The LNA finds its application at Portable GPS Receiver, BLE, Zigbee, NFC, WiFi, Wireless Sensor Network, RFIC operating at 2.4GHz frequency. Millimeter wave communication is an evolving technology for bandwidth demanding 5G wireless application. A high gain and linear narrowband cascode Low Noise Amplifier (LNA) operating at 2.18GHz to 2.47GHz is proposed. To demonstrate design methodology, a narrow-band source degenerated cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4 GHZ band. The LNA achieves a voltage gain of 5.38dB, Noise figure of 4.1127dB, and from 3.2 V supply voltage. Proper input and output impedance matching have been performed to achieve the input return loss of -14 dB (S11) and output return loss of -19.72 dB (S22). Simulation study has been done using Cadence spectre.

A A 57-64 GHz High-gain Amplifier using Ultra-wideband Inductors in the IMNs and Optimization by PCA and SDSM

In this paper, the design and optimization of a cascaded common source four-stage millimeter wave amplifier in a 130 nm CMOS technology has been presented. First, Pi-shaped wideband impedance matching networks (IMNs) were used in the input / output impedance matching networks (IOIMNs) and inter-stages. Next, single stubs were converted to symmetrical double stubs in the IOIMNs and an ultra-wideband inductor replaced each stub. Ultra-wideband inductors were also used in series in the inter-stage IMNs to achieve higher gain in wider frequency bandwidth. Then, the impedance matrices of IOIMNs and inter-stages were calculated using planar circuit analysis (PCA), which is based on the planar waveguide model and segmentation/desegmentation methods (SDSM). Finally, by optimizing the length and characteristic impedance of each segment of microstrip line in the IMNs through using an intelligent algorithm in MATLAB, the excellent IMNs were designed, which resulted in an amplifier with &nbsp;, &nbsp;and &nbsp;in the frequency range of 57- 64 GHz. With this design method, in addition to incorporating the effect of discontinuities, the fringing fields at the edges of the microstrip as well as the conductor and dielectric losses, the effects of dispersion would be minimized by choosing a substrate whose thickness is much smaller than the wavelength and its relative permittivity is low.

A 6 GHz Integrated High-Efficiency Class-F−1 Power Amplifier in 65 nm CMOS Achieving 47.8% Peak PAE

This paper reports a “single-transistor” Class-F−1 power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F−1 harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F−1 harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB.

An Optimal Design of High Output Power CMOS Class E Power Amplifier with Broadband Matching for RFID Applications

In the radio frequency frontend the power amplifiers are most essential block for reliable wireless communication. Power amplifiers are used for amplification and enhance the input signal to the desired power level at output. The class-E power amplifiers are used in many RF portable electronic devices that need low power consumption, high gain, and high efficiency. In this article, we present an optimum design of a complementary metal-oxide semiconductor (CMOS) class-E power amplifier (PA) that achieves high efficiency and high gain simultaneously for RF based electronic article surveillance (EAS) system. The simulated analysis and implementation of a class-E RF power amplifier with an appropriate output impedance matching network are presented. The proposed CMOS class-E PA has 41.7 dBm output power with 63% of power efficiency at frequency of 7.7 MHz to 8.7MHz.

A Fast-Dynamic Control Scheme for a Power-Electronics-Based PV Emulator

The dynamic performance of a photovoltaic (PV) emulator is critical for testing applications with fast maximum power point tracking (MPPT) algorithms. In this article, a power-electronics-based PV emulator (PVE) is proposed to achieve fast-dynamic response, as well as, to emulate accurately in all regions of the current-voltage (I-V) characteristic curve. The control scheme of the proposed PVE consists of an instantaneous output impedance matching (IOIM) controller based on load resistance feedback to generate the voltage reference signal and an inner boundary control (BC) scheme to regulate the converter at a given reference within a short period of time. The IOIM controller overcomes the drawback of conventional PVEs that suffer from oscillating reference signal in a certain region of the I-V characteristic curve. Moreover, use of load resistance feedback in the reference generation algorithm allows the decoupling of the reference signal generator from the inner control loop. The BC scheme adapts a corrected second-order switching surface to achieve a faster response time and robust operation with switching converter loads. Detailed small signal model of the PVE is derived to design the IOIM control loop and to ensure a stable and fast convergent emulation in the entire I-V characteristic curve. Experimental results of a 130 W (VMPP = 35.2 V, IMPP = 3.69 A) prototype are presented with both resistive loads and an MPPT converter to verify its performance under fast varying irradiance and load conditions.

A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-mode transmitter (TX) with a four-tap feed-forward equalizer (FFE). A two-step coarse-/fine-tuning technique is adopted in the voltage-mode FFE to reduce the number of front-end slices while maintaining sufficient resolution. In addition, the device sizes in the preceding multiplexer (MUX) and predriver can be enlarged, relaxing the self-loading effect from the layout and improving the bandwidth. An analog impedance control loop is applied to achieve output impedance matching and maintain the corresponding weighting between coarse- and fine-FFE stages. The quarter-rate 4:1 MUX incorporates an automatic phase alignment technique to eliminate the timing constraint. As a result, all of the retiming latches can be removed, saving significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX demonstrates a high-quality eye diagram at 112 Gb/s with 3.89-pJ/b energy efficiency under a chip-on-board assembly with 5.5-dB Nyquist loss.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

A 0.3–6 ​GHz noise and distortion cancelling LNA achieving an NF of 2.8±0.3 ​dB in 0.18-μm SiGe BiCMOS process

This paper presents a noise and distortion cancelling wideband low-noise amplifier (LNA) in JAZZ 0.18-μm SiGe BiCMOS process. In the proposed design, a shunt feedback (SFB) and a common-emitter (CE) paths are adopted to reduce the dominant noise contribution of the main path. To enhance the linearity, the derivative superposition method is modified to eliminate the whole nonlinearity components. Moreover, with the help of an n-type MOS acted as a resistive load of the CE path, both flat gain and acceptable output impedance matching are achieved. The measurement results exhibit that the LNA has an input third-order intercept point (IIP3) of −4 dBm with a noise figure (NF) of 2.8 ​± ​0.3 ​dB and a power gain 16.5 ​± ​0.2 ​dB from 0.3 to 6 ​GHz. The circuit draws 14.5 ​mA dc current from a 3.3 ​V supply for core area of 0.22 ​mm2.

The Design of an Ultra-Low-Voltage Ultra-Low-Power 7.5 GHz LNA in 0.13µm CMOS Technology

In this paper a low noise amplifier (LNA) is designed at 7.5 GHz with ultra-low power consumption in 0.13µm CMOS technology. New and precise calculations for input and output impedance are calculated and compared with other works. The forward body biasing technique is utilized to bring down power consumption of the circuit. MATLAB, HSPICE, Advanced Design System (ADS), and TSMC 0.13 µm CMOS process are used to simulate the LNA. The performance of the circuit is scrutinized with and without spiral inductors. With lumped inductors, 0.42 dB, -27dB, -4dB, 20dB, 156µW, and -3 are achieved for noise figure (NF), input impedance matching (S11), output impedance matching (S22), power gain (S21), power consumption, and the third order intercept point (IIP3) respectively. Plus, with spiral inductors 2.3dB, -23dB, -5dB, 10dB, 156µW, and -7 are achieved for noise figure (NF), input impedance matching (S11), output impedance matching (S22), power gain (S21), power consumption, and the third order intercept point (IIP3) respectively.

A 0.5 to 6 GHz wideband cascode LNA with enhanced linearity by employing resistive shunt‐shuntfeedback and derivative superposition

AbstractA wideband bipolar low‐noise amplifier (LNA) with enhanced linearity operating in 0.5 to 6 GHz frequency range is proposed in this letter. The LNA design is based on a cascode amplifier with an emitter degeneration RC parallel network and a resistive shunt‐shunt feedback which can improve linearity. The cascode topology in conjunction with the preceding series inductor L is utilized to achieve good wideband input impedance matching, while the wideband output impedance matching is realized by using an emitter follower as a buffer. And the third‐order input intercept point (IIP3) has been improved due to the derivative superposition technique. The wideband LNA presented in this letter was designed and implemented in a JAZZ 0.18 μm SiGe BiCMOS process. The measured results show that from 500 MHz to 6 GHz, the power gain (S21) is 16.5 to 17.1 dB, the noise factor (NF) is 2.7 to 3.3 dB, the current consumption without buffer stage is 12.4 mA at a 3.3 V supply voltage, and the IIP3 is −0.834 dBm at 2 GHz. The chip size is 1.06 × 0.64 mm2.

New noise cancellation topology in common-gate LNAs

In this paper a new approach for designing noise canceling common gate (CG) low noise amplifiers (LNAs) is proposed. This method investigates using inductively degenerated common source (IDCS) stage in parallel with CG stage instead of common source (CS) stage. Considering special specification of IDCS LNA, proposed topology can achieve lower noise figure (NF) and better input impedance matching. Analytical calculation for this topology is performed and the equations to satisfy input impedance matching along with noise cancellation condition are presented. The NF of proposed LNA is also calculated while satisfying these conditions by using the calculation of each noise source's transfer function. To validate theoretical analysis, two different LNAs in X band are designed and optimized. The simulations are performed using Advanced Design System (ADS) electromagnetic momentum with GaAS pHEMT 0.1 μm process model. The results shows the proposed method can achieve better input impedance matching and lower NF while the output impedance matching and gain have relatively the same behavior.

Miniaturised wideband four‐way out‐of‐phase power divider based on Marchand balun

A miniaturised wideband four-way out-of-phase power divider is presented in this study. The presented divider is developed based on a microstrip-line Marchand balun, which achieves the power-dividing function through the coupling between parallel microstrip lines (MLs). The coupling performance is improved by etching the rectangular-ring slots under the coupled MLs, which improved the operating bandwidth. The air-bridge resistance isolation circuit is used to improve the output impedance matching and isolation. Moreover, the even- and odd-mode equivalent-circuit method is applied to the presented power divider. The design has been verified by measurements, which show good agreements with simulations. The measured results show that the centre frequency is 3.4 GHz, the 15 dB input return loss bandwidth is >59.6%, and the output isolation is >15 dB.

Analysis and design of multi-stage wideband LNA using simultaneously noise and impedance matching method

An analytical approach for design optimization of multi-stage LNAs with common source topology is developed. This paper reviews and analyses simultaneous noise and input impedance matching in three different topologies including common source amplifier with inductive degeneration, resistive feedback and dual feedback in order to achieve maximum available gain and minimum possible noise figure (NF). A study on multi-stage LNAs is performed to calculate optimum input impedance of each stage for minimum overall NF while considering the gain and NF of that stage in addition to the effect of noise of the following stages. MATLAB was used to calculate the starting point of design optimization in a multi-stage LNA. The proposed LNA in 0.1-μm GaAs pHEMT process exhibits a gain of 28 dB in the bandwidth of 3 GHz, input impedance matching of −14 dB, output impedance matching of −12 dB and 1-dB gain compression point of 10 dBm.

W-band low-noise amplifier using λ/2-spiral-inductor-based positive feedback technique in 90 nm CMOS

A low-power and wideband low-noise amplifier (LNA) for 77 GHz automobile radar and 94 GHz image radar systems using 90 nm CMOS technology is reported. Half-wavelength (λ/2)-spiral-inductor-based positive feedback technique is used at the common-source input stage for gain (S21) enhancement. Moreover, T-match technique is utilized to achieve simultaneously wideband input and output impedance matching, and wideband S21 and noise figure (NF). The LNA consumes 6.3 mW and achieves S11 and S22 better than − 10 dB for frequencies of 76.9–94.1 GHz and 77.2–96.7 GHz, respectively. That is, the corresponding input and output matching bandwidth are 17.2 GHz and 19.5 GHz, respectively. Additionally, high and flat S21 of 13.5 ± 1.5 dB is achieved for frequencies of 77–99.5 GHz, which means the corresponding 3-dB bandwidth is 22.5 GHz. Furthermore, the LNA achieves NF of 6.3–8.1 dB for frequencies of 75–100 GHz and excellent FOM (figure-of-merit) of 5.97 GHz/mW, one of the best results ever reported for a CMOS LNA with similar operation frequency.