Output Frequency Range Research Articles

The design of a wide bandwidth time marker generator.

The Time Marker Generator (TMG) is an important instrument that is used to calibrate the time base of an oscilloscope. If a direct digital frequency synthesizer is used to generate the necessary waveforms, there is serious distortion in the generated square wave when the ratio of the sampling frequency to the output frequency is non-integer. In addition, the look-up table (LUT) in the direct digital waveform synthesizer needs a large storage capacity to generate a narrow triangular wave at a low output frequency. This paper proposes a design that will generate the time marker whose samples are synthesized by real-time calculation instead of storing them in a LUT. We also propose an M waveform data synthesizer with a parallel structure (M-WDSPS) to reduce the operating clock frequency of the field programmable gate array (FPGA). We built a 4-WDSPS TMG based on this design and reduced the required clock frequency from 1 GHz to 250 MHz, thus making the implementation possible in an FPGA. Our proposed TMG design can provide square wave, pulse wave, narrow triangular wave, and linear triangular wave with different amplitudes in two operating modes: normal mode and highlight mode. The TMG we constructed can provide the time marker with an output frequency range from 10 mHz to 111 MHz, a rising/falling edge time lower than 1 ns, regardless of whether the output frequency is low or high, and a frequency stability lower than 0.1 ppm.

On the Potential Application of Direct Digital Synthesis in the Development of Frequency Synthesizers for Quantum Frequency Standards

A new method for generation of the output signal of a frequency synthesizer of quantum frequency standards is considered. It is demonstrated that this method provides an opportunity to enhance spectral characteristics of the output signal, expand the range of output frequencies, and reduce the tuning step of the output frequency. A considerable (more than 10%) improvement in the frequency stability of a cesium-133 quantum standard and a 2.4-fold improvement in its temperature coefficient of frequency are reported.

Ins, Outs of Frequency-lowering Processing

Ins, Outs of Frequency-lowering Processing

Reduction of the Phase Noise Level of Heterodynes of Modern Spectrum Analyzers Using Fundamental Frequency Images of Direct Digital Synthesizers

A hybrid frequency synthesizer ins developed in which fundamental frequency images of a direct digital synthesizer are used to improve noise characteristics. It is shown that this synthesizer can generate a wide range of output frequencies with a small step size adjustment. Mathematical modeling of the noise characteristics of the synthesizer and comparison with the noise characteristics of heterodynes of modern spectrum analyzers are carried out.

A Dual-Loop Synthesizer With Fast Frequency Modulation Ability for 77/79 GHz FMCW Automotive Radar Applications

The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task. The frequency modulation dynamics are analyzed for this architecture. The results are employed to implement a SiGe BiCMOS fully integrated 75–83 GHz frequency-modulated continuous-wave synthesizer. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism together with the dual-loop PLL architecture provides low loop bandwidth variation over the whole output frequency range, −97 dBc/Hz phase noise at 1-MHz offset, and maximal modulation rate of 100 GHz/ms.

Research on High Performance Frequency Synthesizer in Radio Frequency Integrated Circuits

With the popularization of broadcasting networks, telecommunication networks, and Internet triple play services, broadband requirements have been proposed for transceivers in wireless communication systems. Frequency source is an important part of the RF transceiver, which is usually chosen as the source of the transceiver frequency reference source. Therefore, the development of ultra-wideband, high stability, low phase noise, and low spurious performance of the frequency synthesizer is of great significance. This paper firstly analyzed the transmission process of noise in phase-locked loop by establishing a linear mathematical model of phase locking loop (PLL), and then studied the main factors affecting the phase noise and spurious performance in the application design. In order to meet the demand of triple-miniaturized RF front end, an integrated phase-locked chip is used to design a frequency synthesizer, where the output frequency of the two channels ranges from 137.5 MHz to 4.4 GHz. In order to meet the engineering application requirements, the frequency synthesizer is designed with a host computer to achieve the programmable control of the output frequency and output power. Finally, the optimized design of a wideband frequency synthesizer is provided to make up for the lack of performance of the integrated phase-locked chip design, of which the output frequency range is 31.25 MHz ~8 GHz, including basic PLL module circuit, power control module circuit, and frequency expansion module circuit.

Design of a High-Sensitivity Ambient Particulate Matter 2.5 Particle Detector for Personal Exposure Monitoring Devices

This paper newly proposes a high-sensitivity ambient particulate matter 2.5 (PM2.5) particle detector for personal exposure monitoring devices. The proposed high-sensitivity ambient PM2.5 particle detector compactly combined a commercial dust sensor and a complementary metal-oxide-semiconductor transducer. The measured PM2.5 concentration ranged from 6.64 to $55.12~\mu \text{g}$ /m3, and the corresponding output frequency range of the proposed particle detector was 0.63 to 4.03 MHz. The sensitivity was 70.287 kHz/( $\mu \text{g}$ /m3), which is largely upgraded compared with prior arts. All the functions and performance of the proposed particle detector for personal exposure monitoring devices were correctly verified and proven through measurements. An open-air experiment for monitoring PM2.5 concentration in industrial park was also tested successfully. The design of the proposed high-sensitivity ambient PM2.5 particle detector was suitable for personal exposure monitoring devices.

Integration of acoustic and electric hearing is better in the same ear than across ears

Advances in cochlear implant (CI) technology allow for acoustic and electric hearing to be combined within the same ear (electric-acoustic stimulation, or EAS) and/or across ears (bimodal listening). Integration efficiency (IE; the ratio between observed and predicted performance for acoustic-electric hearing) can be used to estimate how well acoustic and electric hearing are combined. The goal of this study was to evaluate factors that affect IE in EAS and bimodal listening. Vowel recognition was measured in normal-hearing subjects listening to simulations of unimodal, EAS, and bimodal listening. The input/output frequency range for acoustic hearing was 0.1–0.6 kHz. For CI simulations, the output frequency range was 1.2–8.0 kHz to simulate a shallow insertion depth and the input frequency range was varied to provide increasing amounts of speech information and tonotopic mismatch. Performance was best when acoustic and electric hearing was combined in the same ear. IE was significantly better for EAS than for bimodal listening; IE was sensitive to tonotopic mismatch for EAS, but not for bimodal listening. These simulation results suggest acoustic and electric hearing may be more effectively and efficiently combined within rather than across ears, and that tonotopic mismatch should be minimized to maximize the benefit of acoustic-electric hearing, especially for EAS.

Design of a CMOS Chlorophyll Concentration Detector Based on Organic Chlorophyll Battery for Measuring Vegetable Chlorophyll Concentration

In this paper, a CMOS chlorophyll concentration detector based on organic chlorophyll battery for measuring vegetable chlorophyll concentration is newly proposed. The organic chlorophyll battery and analog processing circuits are compactly and robustly cooperated. Comparing with previous works, the proposed chlorophyll concentration detector can be possibly easy and low-cost realized by users. All the functions and performance of the proposed chlorophyll concentration detector for measuring vegetable chlorophyll concentration are successfully tested and proven through measurements. The measured chlorophyll concentration of spinach ranges from 25 to $475~\mu $ mol/ $\text{m}^{2}$ , and the corresponding output frequency range is 599.2 kHz–1.174 MHz. The proposed chlorophyll concentration detector is suitable for devices measuring vegetable chlorophyll concentration.

A 2.4–3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique

This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL includes three main circuit blocks: one-oscillator-period constant-delay (OOPCD) divider, timing-adjusted phase detector (TPD), and pulse generator (PG). The proposed injection timing alignment technique can align the injection timing adaptively in a wide range of the output clock frequency using the two blocks (OOPCD and TPD) and a falling edge locking scheme of pulses. It can avoid the risk that SILPLL may lock to the wrong frequency or even fail to lock. The PG block is used for half-integral injection to relax the tradeoff between the phase noise of SILPLL and the output frequency resolution. The OOPCD circuit occupies a negligible area. After the injection timing alignment is finished, the OOPCD is powered off so that no extra power is consumed. The SILPLL is implemented in the 65-nm 1P9M CMOS process. It consumes 8.6 mW at 1.2 V supply and occupies an active core area of $1 \times 0.6$ mm2. The measured output frequency range is 2.4~3.6 GHz with an output frequency resolution of 200 MHz and the phase noise is −127.6 dBc/Hz at an offset of 1 MHz from a carrier frequency of 3.4 GHz. The rms jitter integrated from 1 kHz to 30 MHz is less than 112 fs for all the covered frequency points. Under the supply voltage range from 1.1 to 1.3 V and the temperature range from −20 °C to 70 °C, the rms jitter variation of all the covered frequency points is less than 27 fs, which shows good robustness over environmental variation.

A 0.2–1.45-GHz Subsampling Fractional- $N$ Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection

A digital fractional-N subsampling multiplying delay-locked loop is proposed in this paper. A zero phase-offset latch-based aperture phase detector is introduced in a reference spur cancellation loop to precisely cancel any static phase offset (SPO) between the injected reference and the digitally controlled oscillator (DCO) phases. An in situ detection scheme is employed to directly measure this phase offset accurately by obviating the requirement of a high-speed off-chip measurement setup. Moreover, a mathematical expression is derived for the calculation of reference spur generated from a given SPO. A uniformly distributed switched capacitor-based DCO frequency tuning achieves highly linear gain. The chip prototype is fabricated in a 1.2-V supply, 65-nm LP CMOS technology and covers an output frequency range of 0.2-1.45 GHz while occupying a core area of 0.054 mm 2 . Measured phase noise at 1.4175 GHz is -95 dBc/Hz at 100-kHz offset, which is 9 dB lower than in phase-locked loop mode of operation.

0.012 mm 2 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps rms integrated jitter in 28 nm FD‐SOI

A multi-protocol PLL suitable for different wireline standards namely HDMI1.4, USB2.0, DDR4, DisplayPort1.2 and for host clock generation for low-power system-on-chips is presented. The PLL employs automatic VCO gain and charge-pump current calibration circuits to provide a near constant PLL bandwidth which enables a robust jitter performance across process, voltage, temperature. Without increasing the loop-filter capacitor, dual-path loop-filter technique is employed to reduce output jitter due to thermal noise of loop-filter resistor. The PLL designed in 28 nm fully depleted silicon on insulator (FD-SOI) process has an output frequency range from 0.1 to 6.4 GHz, total rms integrated jitter of 14 ps at 21.25 MHz reference frequency, consumes 800 μW at 3.4 GHz VCO frequency and occupies an area of 0.012 mm 2 .

Design of a Gas Sensor Transducer Circuitry With Calibration Ability for CO2 Concentration Detection

In this paper, a gas sensor and the proposed calibration chip are presented. For this paper, a commercially available MG811 CO2 gas sensor is used. The output of the CO2 gas sensor was inputted to the proposed chip, and the output signal of the chip is a pulse stream with its frequency corresponding to gas concentration. All functions of the CO2 gas sensor and the proposed chip have been validated experimentally. After calibration, the concentration range of 426–1359 ppm corresponded to the output frequency range of 285–242 kHz. The measured maximum frequency error was 1.3%.

SPD를 이용한 2.4 GHz PLL의 위상잡음 분석

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

Development of a Calibrated Transducer CMOS Circuit for Water Turbidity Monitoring

In this paper, a calibrated transducer CMOS circuit for water turbidity monitoring is proposed. The output signal is a pulse stream. It can be easily broadcast over various digital transmission media. In addition, the proposed calibration method can reduce nonlinear errors arising from turbidity sensors. The turbidity of 8-1011 nephelometric turbidity units corresponded to the output frequency range of 25.3-22.3 kHz. After calibration, measured maximum frequency error was 0.36%.

A 0.0054-mm2Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor

In this brief, a frequency-to-current conversion-based fractional frequency synthesizer is implemented in 32-nm technology utilizing a high-density deep trench capacitor. The technique proposed here can replace the use of multiple crystal oscillators or a phase-locked loop for medium accuracy clock generation with very low chip area and power consumption. In addition to exploiting the inherently low variation of capacitors as compared to that of transistors, the proposed circuit generates an output frequency proportional to the capacitor ratio, canceling out any small process-voltage-temperature (PVT) dependences of the capacitor. The performance of the fractional synthesizer is verified from chip measurement results. An output frequency range of 16–156 MHz is covered with a frequency resolution of 0.8 MHz using a 4-MHz reference clock. The total area of the frequency synthesizer core is only 0.0054 mm2, and it consumes 116 $\mu\mbox{W}$ of power from a 0.9-V supply while generating an output frequency of 48 MHz. The output frequency variation is ±0.14% at 48 MHz for a temperature sweep from −40 °C to 90 °C. Periodic jitter measured from an on-chip high-resolution jitter measurement circuit is 115 ps (rms) at 76 MHz.

CMOS oscillator with MOS varactor and body bias tuning

In this paper, designs of voltage controlled oscillator (VCO) using three transistors XNOR gates with variable capacitive load have been presented. Three and five stage VCO circuits have been designed using the concept of reverse body bias and variable NMOS load. The tuning of output frequency has been controlled by coarse and fine tuning methods. Coarse tuning has been achieved with the variation in supply voltage from 1.8 V to 3 V and fine tuning has been obtained with variation in reverse bias voltage of NMOS load from 0 V to −0.8 V. A tuning range of 20% and 19% have been obtained with the proposed three and five stages VCO circuits. Results have been obtained for 0.18 µm CMOS technology. Power consumption and output frequency range of proposed VCO circuits have been compared with earlier reported circuits and proposed circuit's shows improved performance.

Frequency stability and phase noise performance of X‐band to Ka‐band active multiplier

The performance of an active frequency doubler used to generate a pump signal for a solid-state microwave amplification by stimulated emission of radiation (MASER) based on paramagnetic impurity ions in sapphire is reported. The frequency doubler has been characterised in terms of phase noise, power dependence and frequency stability (Allan variance) for an output frequency range between 20 and 40 GHz. With the measurement system referenced to a 10 MHz hydrogen MASER, the doubler exhibits a single sideband phase noise of ∼−108 dBc/Hz at 1 Hz offset frequency, from which an upper limit fractional frequency instability of about 2 × 10−16 at 1 s integration time is estimated.

Design and analysis of a K‐band wideband voltage‐controlled oscillator with robust start‐up and frequency boost

This study presents a K-band differential voltage-controlled oscillator (VCO) with robust start-up. A hybrid technique that combines open-loop digitally controlled tail current with switchable auxiliary cross-coupled pairs (ACCPs) is proposed to ensure robust start-up for wideband operation. Compared with prior closed-loop current controlling method, the proposed technique does not suffer from phase-noise degradation. Furthermore, by evenly distributing the ACCPs, transistors with smaller size are allowed to achieve the same start-up condition, which leads to frequency boost and phase-noise improvement. Implemented in 0.18 μm complementary metal–oxide–semiconductor technology, the VCO achieves a wide-frequency tuning range of 21.4–26.29 GHz (20.5%) and a low phase noise of −108.8 dBc/Hz at 1 MHz offset from 25.8 GHz carrier frequency. At 1.1 V power supply, the power consumption of the core circuit is 7.9–11.4 mW across the entire output frequency range.

A low-jitter third-order self-biased PLL with adaptive fast-locking scheme for SerDes interfaces

This paper presents a 3rd-order self-biased phase-locked loop (PLL) with adaptive fast-locking scheme for serialize/deserialize (SerDes) interfaces. In order to obtain short and almost equal power-up latency in a wide range of reference frequencies, a fast-locking circuit block including 2 switched-capacitor frequency-to-voltage (F---V) converters and an adaptive discharger is proposed to speed up the power-up process. Additionally, the current in the charge pump (CP) of the traditional self-biased PLL tends to be influenced by the kick-back noise from the voltage-controlled oscillator (VCO). In order to reduce the jitter resulted from the VCO kick-back noise, an additional bias generator is inserted between the original bias generator and the VCO to isolate the bias signals for the CP and the VCO. The simulated clock jitter under 100-mV, 1-MHz supply noise is 27 ps at an output frequency of 2 GHz, which is much lower than that of the traditional counterpart. The presented PLL is integrated in a SerDes interface chip fabricated in a 0.25-μm standard CMOS technology. Measurement results show that the presented PLL achieves a power-up latency of 4---6.5 μs in the output frequency range of 200 MHz---2 GHz, and the peak-to-peak data jitter of the SerDes chip is 110 ps at a data rate of 2.5 Gbps. The presented PLL consumes 217 mW under a 2.5-V power supply, and the block area is 350 × 600 μm2.