Output Error Probability Research Articles

Distribution consensus of nonlinear stochastic multi-agent systems based on sliding-mode control with probability density function compensation

Strict consensus is difficult to be implemented due to the stochastic behavior of multi-agent systems (MASs), so a new concept, distribution consensus, is proposed here to keep the agents’ consensus in the stochastic sense, i.e., the output errors do not converge to a fixed value but follow a desired distribution function. The appropriate control protocol, with the output error probability density function (PDF) as the target, is designed based on the combination of sliding mode control and PDF compensation. Sliding mode control is the core part to ensure the whole system’s stability, and the PDF compensator is used to compensate the random variation and reduce the chattering effect, respectively. In order to realize the complete control in real time, the PDF compensator is modeling by a radial basis function (RBF) neural network and its optimal control law is calculated by the iterative training of RBF network weights. Finally, the effectiveness of the proposed method is verified by MASs simulations with three different communication topologies. The PDF compensator can greatly improve the consensus effect for the nonlinear stochastic MASs.

Asymptotically Linear Analysis and Gate Probability Allocation Schemes in Probabilistic Circuits

As the feature size of CMOS technology rapidly shrinks into the very deep submicrometer, the power density is getting higher and the circuit's reliability is seriously impacted by thermal noise. In order to reduce power dissipation, decreasing the supply voltage is a promising way. However, soft errors and decreased supply voltage make circuits behave probabilistic. Fortunately, some applications can tolerate a certain level of operation errors. The tradeoff between energy and reliability provides an opportunity to save the power consumption in the circuit. An asymptotically linear analysis (ALA) strategy is proposed to model the reliability evaluation of combinational logic circuits. Under the assumption that the gate error probability is not more than 0.05, an asymptotic linear matrix A is constructed by using the first-order term of the output error probability. When propagating the gate error probability from the input to the output ports, the ALA strategy only requires one multiplication between the matrix A and the gate error probability vector. There are significant differences in the complexity of computation of the ALA scheme and the Bayesian network (BN) and the probability transfer matrix (PTM) schemes, while its relative error (RE) is no more than 0.08 on the benchmark of LGSynth91. Furthermore, three schemes are proposed to adjust the gate error probability to meet the constraint on the error probability of the probabilistic CMOS (PCMOS) circuit's outputs. The proposed schemes can be performed to search the gate error probability combinations in the logic and circuit design stage of VLSI. During the power optimization, the switching activity factor in the asymptotically linear region is approximately invariant. It makes the power optimal model convex. The energy-saving ratio of the proposed power optimization scheme is 5%-6% higher than the existing schemes. The time consumption of the proposed three schemes is one-thousandth of the time consumed by the BN and PTM schemes. All the three schemes are verified by conducting experiments on the ISCAS'85 and IWLS'15 benchmark circuits. The simulation results establish the feasibility of the ALA and the performance of the proposed schemes.

Generalized error-locating codes with component codes over the same alphabet

We consider generalized error locating (GEL) codes over the same alphabet for both component codes. We propose an algorithm for computing an upper bound on the decoding error probability under known input symbol error rate and code parameters. Is is used to construct an algorithm for selecting code parameters to maximize the code rate for a given construction and given input and output error probabilities. A lower bound on the decoding error probability is given. Examples of plots of decoding error probability versus input symbol error rate are given, and their behavior is explained.

Generalized error-locating codes and minimization of redundancy for specified input and output error probabilities

Generalized error-locating codes are discussed. An algorithm for calculation of the upper bound of the probability of erroneous decoding for known code parameters and the input error probability is given. Based on this algorithm, an algorithm for selection of the code parameters for a specified design and input and output error probabilities is constructed. The lower bound of the probability of erroneous decoding is given. Examples of the dependence of the probability of erroneous decoding on the input error probability are given and the behavior of the obtained curves is explained.

Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach

Transient faults in logic circuits are becoming an important reliability concern for future technology nodes. Radiation-induced faults have received significant attention in recent years, while multiple transients originating from a single radiation hit are predicted to occur more often. Furthermore, some effects, like reconvergent fanout-induced glitches, are more pronounced in the case of multiple faults. Therefore, to guide the design process and the choice of circuit optimization techniques, it is important to model multiple faults and their propagation through logic circuits, while evaluating the changes in error rates resulting from multiple simultaneous faults. In this paper, we show how output error probabilities change with increasing number of simultaneous faults and we also analyze the impact of multiple errors in state flip-flops, during the cycles following the cycle when fault(s) occurred. The results obtained using the proposed framework show that output error probability resulting from multiple-event transient or multiple-bit upsets can vary across different outputs and different circuits by several orders of magnitude. The results also show that the impact of different masking factors also varies across circuits and this information can be valuable for customizing protection techniques.

Probabilistic Error Modeling for Nano-Domain Logic Circuits

In nano-domain logic circuits, errors generated are transient in nature and will arise due to the uncertainty or the unreliability of the computing element itself. This type of errors - which we refer to as dynamic errors - are to be distinguished from traditional faults and radiation related errors. Due to these highly likely dynamic errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic. We propose a probabilistic error model based on Bayesian networks to estimate this expected output error probability, given dynamic error probabilities in each device since this estimate is crucial for nano-domain circuit designers to be able to compare and rank designs based on the expected output error. We estimate the overall output error probability by comparing the outputs of a dynamic error-encoded model with an ideal logic model. We prove that this probabilistic framework is a compact and minimal representation of the overall effect of dynamic errors in a circuit. We use both exact and approximate Bayesian inference schemes for propagation of probabilities. The exact inference shows better time performance than the state-of-the art by exploiting conditional independencies exhibited in the underlying probabilistic framework. However, exact inference is worst case NP-hard and can handle only small circuits. Hence, we use two approximate inference schemes for medium size benchmarks. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results. We have performed our experiments on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LGSynth'93</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ISCAS'85</i> benchmark circuits. We explore our probabilistic model to calculate: 1) error sensitivity of individual gates in a circuit; 2) compute overall exact error probabilities for small circuits; 3) compute approximate error probabilities for medium sized benchmarks using two stochastic sampling schemes; 4) compare and vet design with respect to dynamic errors; 5) characterize the input space for desired output characteristics by utilizing the unique backtracking capability of Bayesian networks (inverse problem); and 6) to apply selective redundancy to highly sensitive nodes for error tolerant designs.

Cell architecture for nanoelectronic design

Nanotechnology research has already proved and implemented several nanoscale devices. However, due to high defect ratios, large parameter variability and reduced noise margins, special architectures are needed to build reliable mid/large nanocircuits. Up to date several architectures have been proposed to design circuits in the nanoscale, but they do not consider the entire nanoscale environment. In this work, we propose and analyze a cell architecture based on the averaging of multiple nanodevices which is capable of alleviating the three main problems of the nanodevices at the gate level (internal noise, device parameter variation and defects). The proposed structure has a low implementation complexity which further reduces the fabrication defects. Using this cell architecture we present 2 and 3-input NAND gates showing their output response and error probabilities. Finally, we show that it is possible to improve the cell error tolerance by taking advantage of interferences among nanodevices which reduces the standard deviation by a factor larger than N.

Effects of Spatial Correlation on MIMO Adaptive Antenna System With Optimum Combining

In this paper, we investigate the effects of the spatial fading correlation on the performance of a multiple-input multiple-output (MIMO) adaptive antenna system with optimum combining (OC) in the presence of multiple cochannel interferers over a correlated Rayleigh fading channel. Based on the Khatri's distribution functions of quadratic forms in complex Gaussian random matrices, we develop a unified determinant representation of those joint eigenvalue distributions. Taking into account the spatial correlation among the antenna elements at the transmitter or receiver, we derive the closed-form formulas for the probability density function and outage probability of the maximum output signal-to-interference ratio (SIR) in an interference-limited MIMO-OC system. Furthermore, the average output SIR and error probability are also investigated. From numerical examples, we show that a new theoretical approach gives a simple and accurate way to assess the performance of the MIMO-OC system over arbitrarily correlated fading channels

Error Exponents for Recursive Decoding of Reed–Muller Codes on a Binary-Symmetric Channel

Error exponents are studied for recursive decoding of Reed-Muller (RM) codes and their subcodes used on a binary-symmetric channel. The decoding process is first decomposed into similar steps, with one new information bit derived in each step. Multiple recursive additions and multiplications of the randomly corrupted channel outputs plusmn1 are performed using a specific order of these two operations in each step. Recalculated random outputs are compared in terms of their exponential moments. As a result, tight analytical bounds are obtained for decoding error probability of the two recursive algorithms considered in the paper. For both algorithms, the derived error exponents almost coincide with simulation results. Comparison of these bounds with similar bounds for bounded distance decoding and majority decoding shows that recursive decoding can reduce the output error probability of the latter two algorithms by five or more orders of magnitude even on the short block length of 256. It is also proven that the error probability of recursive decoding can be exponentially reduced by eliminating one or a few information bits from the original RM code

Recursive error correction for general Reed–Muller codes

Reed–Muller (RM) codes of growing length n and distance d are considered over a binary symmetric channel. A recursive decoding algorithm is designed that has complexity of order n log n and corrects most error patterns of weight ( d ln d ) / 2 . The presented algorithm outperforms other algorithms with nonexponential decoding complexity, which are known for RM codes. We evaluate code performance using a new probabilistic technique that disintegrates decoding into a sequence of recursive steps. This allows us to define the most error-prone information symbols and find the highest transition error probability p , which yields a vanishing output error probability on long codes.

Soft-decision majority decoding of Reed-Muller codes

We present a new soft-decision majority decoding algorithm for Reed-Muller codes RM(r,m). First, the reliabilities of 2/sup m/ transmitted symbols are recalculated into the reliabilities of 2/sup m-r/ parity checks that represent each information bit. In turn, information bits are obtained by the weighted majority that gives more weight to more reliable parity checks. It is proven that for long low-rate codes RM(r,m), our soft-decision algorithm outperforms its conventional hard-decision counterpart by 10 log/sub 10/(/spl pi//2)/spl ap/2 dB at any given output error probability. For fixed code rate R and m/spl rarr//spl infin/, our algorithm increases almost 2/sup r/2/ times the correcting capability of soft-decision bounded distance decoding.

Convolutional Coding for High-Speed Microwave Radio Communications

This paper describes the design, testing, and measured performance of a rate 11/12 self-orthogonal convolutional codec that meets the bit-error-rate objective of M-state quadrature amplitude modulation systems in terrestrial radio transmission. The objective is to reduce a bit error probability of 10−6 to 10−10 or smaller. In fact, the measured output error probability is well below 10−10 when the channel error probability is below 10−5.

Walsh-function representation and noise analysis of linear sequential circuits

Walsh functions are used to characterize the operation of linear sequential circuits. The state and output equations of a linear sequential circuit are converted into recursive matrix equations over the reals that are conceptually simple. This characterization provides an easy way to determine the output statistics for a stochastic input. A noisy environment is simulated by a dyadically additive error process that facilitates the analysis of output error probabilities. A numerical example is given.

Microprocessor-Based Viterbi Decoding of Convolutional Codes

For a short constraint length nonsystematic rate-half convolutional code with a Hamming distance of 5, a Viterbi decoding algorithm using Synertek—6502 microprocessor system has been developed. It has been shown here how the microprocessors can be interfaced to the coded signal from an external encoder and decode the data even in the presence of errors. The flowchart and the memory organization in the microprocessor have been discussed in this paper. Care has to be taken so that the calculated parameters, like the likelihood function does not exceed the word-length of the micro-processor. A throughput data rate of 2400 bps has been achieved with the system. This enables reliable transmission of 1200 bps data after encoding by rate-half error correction code to result in 2400 bps line rate, over telephone channels.It is important to consider the problems of requiring different computation time for different iterations in the decoding and establishing a reference time in the microprocessor to start iteration everytime. These problems have been solved by using the interrupt facilities.Errors have been added to the encoded output signal and the microprocessor-based Viterbi algorithm provided the decoded data correcting upto all patterns of 2 errors in 7 code bits. Experimental tests with random noise show that the decoder reduces the output error probability from 10-3 to 10-6.