Asymptotically Linear Analysis and Gate Probability Allocation Schemes in Probabilistic Circuits

Abstract

As the feature size of CMOS technology rapidly shrinks into the very deep submicrometer, the power density is getting higher and the circuit's reliability is seriously impacted by thermal noise. In order to reduce power dissipation, decreasing the supply voltage is a promising way. However, soft errors and decreased supply voltage make circuits behave probabilistic. Fortunately, some applications can tolerate a certain level of operation errors. The tradeoff between energy and reliability provides an opportunity to save the power consumption in the circuit. An asymptotically linear analysis (ALA) strategy is proposed to model the reliability evaluation of combinational logic circuits. Under the assumption that the gate error probability is not more than 0.05, an asymptotic linear matrix A is constructed by using the first-order term of the output error probability. When propagating the gate error probability from the input to the output ports, the ALA strategy only requires one multiplication between the matrix A and the gate error probability vector. There are significant differences in the complexity of computation of the ALA scheme and the Bayesian network (BN) and the probability transfer matrix (PTM) schemes, while its relative error (RE) is no more than 0.08 on the benchmark of LGSynth91. Furthermore, three schemes are proposed to adjust the gate error probability to meet the constraint on the error probability of the probabilistic CMOS (PCMOS) circuit's outputs. The proposed schemes can be performed to search the gate error probability combinations in the logic and circuit design stage of VLSI. During the power optimization, the switching activity factor in the asymptotically linear region is approximately invariant. It makes the power optimal model convex. The energy-saving ratio of the proposed power optimization scheme is 5%-6% higher than the existing schemes. The time consumption of the proposed three schemes is one-thousandth of the time consumed by the BN and PTM schemes. All the three schemes are verified by conducting experiments on the ISCAS'85 and IWLS'15 benchmark circuits. The simulation results establish the feasibility of the ALA and the performance of the proposed schemes.