Sensitivity analysis of Probability Transfer Matrix (PTM) on same functionality circuit architectures

Abstract

As CMOS technology advances to nano-scale devices, the performance of logic integrated circuits becomes a focal point in current literatures. The circuit's performance measured based on its reliability is not only depending on its gate error probability, p, but it also depends on the architecture of that circuit. Thus, this drives a need to measure and evaluate reliability values for different architectures of same functionality circuit. This paper looks into the performance comparison in terms of reliability measurement for different architectures of same functionality circuits using common reliability evaluation models such as Probabilistic Gate Model (PGM), Boolean Difference-based Error Calculator (BDEC) and Probabilistic Transfer Matrix (PTM). For this purpose, we have chosen C17 and Full Adder as our benchmark test circuits. It has been shown that only PTM model is able to evaluate reliability values for different architectures of C17 and Full Adder circuits whereas PGM and BDEC models depict no change in their reliability values. Simulation results conclude that PTM model has the ability to show its sensitivity to reliability measurement for different circuit architectures of same functionality circuits compared to PGM and BDEC. PTM sensitivity analysis is necessarily significant to circuit designers in producing robust and more reliable nano-scale circuit systems.