Output Capacitor Research Articles

Comparative evaluation of Z source / quasi Z-source direct and indirect matrix converters for PMG based WECS

The present era sees the dominance of wind energy conversion systems as a leading technology in renewable energy. Various technologies have been devised to harness wind energy, with variable speed systems emerging as particularly advantageous. Consequently, these systems are designed to operate at specified speeds using power electronic interfaces, maximizing power extraction from the wind. The integration of Permanent Magnet Generators (PMGs), directly linked to the wind turbine lacking a gearbox, allows operation at minimum speeds. To stabilize the continuously fluctuating output voltage of the PMG, power electronic converters are extensively utilized in Wind Energy Conversion Systems (WECS), ensuring a consistent voltage and frequency output. The voltage gain of Traditional matrix converters (MCs) is limited to less than 0.866. In turn, the Z-source (ZS) and discontinuous QZSDMC, as well as ZS IMCs, topologies have achieved voltage gains exceeding 0.866. However, the former provides complicated commutation issues from DMC, while the latter incorporates a Z source network in the DC link, resulting in a non-all-silicon solution. A novel continuous QZSDMC and QZSIMC are suggested, wherein a qZS network incorporates the grid-side filtering function. This design eliminates the need for an additional input filter in the proposed system. Three newly introduced topologies of ZSDMC, QZSDMC and QZSIMC are thoroughly compared across various parameters including voltage gain, current and voltage ripples, inductor current and capacitor voltage stresses, filtering capabilities, input current, and output voltage Total Harmonic Distortion (THD), finally efficiency. The paper presents their control and modulation methods to achieve the desired performance levels. Experimental comparisons validate the theoretical analysis and demonstrate the potential of the proposed QZSDMC as a promising topology.

A non-invasive capacitive sensor to investigate the Leidenfrost phenomenon: a proof of concept study

A volatile sessile liquid droplet or a sublimating solid manifests levitation on its own vapor when placed on a sufficiently heated surface, illustrating the Leidenfrost phenomenon. In this study, we introduce a non-invasive capacitance method for investigating this phenomenon, offering a potentially simpler alternative to existing optical techniques. The designed sensor features in-plane miniaturized electrodes forming a double-comb structure, also known as an interdigitated capacitor. Initially, the sensor’s capacitance is characterized for various distances between the sensor and a dielectric material. The influence of the sensor substrate material and the spacing between the electrodes on the sensor’s capacitance is also investigated. To demonstrate the feasibility of the method, a sublimating dry ice pellet is placed on the capacitive sensor, and its performance is evaluated. We present results for the dimensionless vapor layer thickness and the pellet’s lifetime at different substrate temperatures, derived from the capacitance output. The results are compared with Optical Coherence Tomography (OCT) data, serving as a benchmark. While the temporal evolution of the sensor’s output, variation in the dimensionless vapor layer thickness, and the lifetime of the dry ice pellet align with expected results from OCT, notable quantitative deviations are observed. These deviations are attributed to practical experimental limitations rather than shortcoming in the sensor’s working principle. Although this necessitates further investigation, the methodology presented in this paper can potentially serve as an alternative for the detection and measurement of Leidenfrost vapor layers.

Dynamic Analysis of the Forward-Flyback Converter Considering the ESR of the Output Capacitor and Comparing it with the Flyback Converter

Dynamic Analysis of the Forward-Flyback Converter Considering the ESR of the Output Capacitor and Comparing it with the Flyback Converter

Output Capacitance Loss of GaN HEMTs in Steady-State Switching

The output capacitance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> ) loss, a loss produced when the device's output capacitor is charged and discharged, has become a concern for GaN high electron mobility transistors (HEMTs) in high-frequency applications. This work presents a new, easy-to-implement method for the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> loss characterization based on the unclamped inductive switching (UIS) setup. As compared to prior approaches, this method involves the device's ON-state conduction and could measure the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> loss in a single pulse and the steady-state switching. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> loss of three types of mainstream commercial GaN HEMTs is characterized, which exhibit some common dependencies including a non-monotonic relation with the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> (or resonance frequency), a linear relation with the ON-state current, a power-law relation with the peak blocking voltage, and little temperature dependence. In addition, their <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> losses all show minimal distinctions in a single pulse and the steady-state switching, despite the increased on-resistance in the steady-state switching. This suggests that the traps accounting for the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> loss possess different de-trapping time constants as compared to the traps governing the dynamic on-resistance. Finally, a unified model is established to describe the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> loss of all three types of GaN HEMTs. These results provide important references for the high-frequency application of GaN HEMTs and new insights into the physical origin of their <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> loss.

Modeling and control of a single-phase grid-tied medium-frequency isolated converter for active and reactive power management in photovoltaic applications

A single-phase photovoltaic converter formed by the full-bridge dc–dc converter with a capacitive output filter and a grid-tied full-bridge inverter is studied in this paper. The switched model, the average model based on a modified-conventional approach, and the linear state-space model of the dc stage operating in discontinuous conduction mode are presented and compared with the behavior of the state variables obtained from a simulator. A duty-ratio constraint is obtained from the modified average model, which is eliminated by expressing its dependency on the control and the state variables. In addition, the modeling of the ac stage is carried out in the dq reference frame. Linear controllers are designed to guarantee the maximum power point tracking, the regulation of the dc-link voltage, the injection of the active power generated, and the reactive power management as an ancillary function. The controllers proposed, according to the transfer functions derived from the linear models, are validated via simulation for a 1.41 kVA converter.

An ANN-Based Output-Error-Driven Incremental Model Predictive Control for Buck Converter Against Parameter Variations

DC/DC buck converters have been widely applied in the power processing of distributed energy resources (DERs) penetrated DC microgrid. Model predictive control (MPC) provides optimal control for the buck converter, but it often requires multiple sensors or complex observers to realize zero-steady-state-error control against parameter variations. An output-error-driven incremental MPC (OEDIMPC) for buck converter is proposed in this paper. Different from the traditional concept of calculating the optimal duty cycle, the proposed MPC calculates the optimal rate of change of the duty cycle by using a reduced-state output-error-driven prediction model. As a result, the OEDIMPC achieves zero-steady-state-error control against parameter variations, including load value, input voltage, output inductor, and output capacitor, with significantly improved dynamic performance and minimal sensor and observer requirements Besides, small- and large-signal analyzes are used to study the stability boundary of the OEDIMPC under parameter variations, and a shallow layer artificial neural network (ANN) is utilized to realize the OEDIMPC on the hardware. The proposed technique has been evaluated experimentally on a buck converter with resistor load and constant power load (CPL), confirming its effectiveness.

Capacitance Analysis for Volume Reduction Based on Integrated Buck and Buck-Boost LED Driver

This paper presents a design methodology to improve the power density of integrated converters operating at universal input voltage fulfilling the standards of connection to the grid and load. The proposed integrated two-stage converter is composed of the power factor correction (PFC) stage behaving as a current source to the bus, and the power control (PC) stage which provides continuous energy to the LED load. Traditionally, the low-frequency ripple (LFR) filtering process is performed by the bus capacitor placed in the output of the PFC stage, while the PC stage output capacitor works only as a high-frequency (HF) filter. The idea is to explore the lower and fixed operating voltage characteristics of the PC stage to share the LFR filtering with the PFC stage. Thus, a mathematical analysis is carried out, considering the influence of the LED characteristics, bus voltage, and capacitances to predict the LFR in the LED current. A case study, composed of an integrated buck and buck-boost converter to supply a 75W LED load, is presented. For the traditional design method, the LED driver needs an 820uF/160V PFC bus capacitor and a 10uF/80V output capacitor to filter the HF components, representing a total capacitors' volume of 17.9cm³. With the proposed analysis, the optimized driver circuit requires a 220uF/160V PFC bus capacitor and a 470uF/80V output capacitor, resulting in a total capacitors' volume of 9.7cm³, providing a volume reduction of approximately 45%.

Unraveling Flow Effect on Capacitive Energy Extraction from Salinity Gradients.

The harvesting of salinity gradient energy through a capacitive double-layer expansion (CDLE) technique is directly associated with ion adsorption and desorption in electrodes. Herein, we show that energy extraction can be modulated by regulating ion adsorption/desorption through water flow. The flow effects on the output energy, capacitance, and energy density under practical conditions are systematically investigated from a theoretical perspective, upon which the optimal operating condition is identified for energy extraction. We demonstrate that the net charge accumulation displays a negative correlation with the water flow velocity and so does the surface charge density, and this causes a nontrivial variation in the magnitude of output energy when water flows are introduced. When high water flows are introduced in both the charging and discharging processes, the energy extraction can be significantly reduced by 47.69-49.32%. However, when a high flow is solely exerted in the discharging process, the energy extraction can be enhanced by 12.94-14.49% even at low operation voltages. This study not only offers a comprehensive understanding of the microscopic mechanisms of surface-engineered energy extraction with water flows but also provides a novel direction for energy extraction enhancement.

Highly efficient reconfigurable double dual quadratic boost converter

ABSTRACT This article synthesises a Double Dual Quadratic Boost (DDQB) converter from a conventional quadratic boost converter. The DDQB’s working principle and steady-state analysis are investigated. The dynamic performance of the DDQB converter is analysed and studied thoroughly. The superiority of the proposed converter is highlighted by comparing it with similar topologies reported in the literature. The advantages of the double dual concept in dc–dc converters over cascaded dc–dc converters are highlighted regarding component stress and power loss reduction. Furthermore, the proposed topology has a low switch count, reduced stresses, and enhanced overall efficiency. The DDQB converter’s gain is eight times for duty cycle D = 0.528 with switch voltage stress of 4.48 times of input voltage, which is not equal to the output voltage of a traditional quadratic boost converter. Additionally, the reconfigured converter with fault-tolerant capability is proposed. In this restructured configuration, single-degree redundancy is studied and analysed for the malfunction of the output capacitor. The performance of restructured configuration is validated in simulation and its reliability is compared with the DDQB converter. Experimentation on a 50 W scaled-down prototype configuration validates the proposed high-gain DDQB topology.

STATCOM Model against SVC Control Model Performance Analyses Technique by Matlab

Principal objective of this paper is to investigate the behavior of STATCOM against SVC controller by setting up new control parameters. Essentially, STATCOM, and SVC linear operating ranges of the V-I and V-Q as well as their functional compensation capabilities have been addressed to meet operational requirement with certain degree of sustainability and reliability. Hereby, the other operating parameters likewise transient stability, response time, capability to exchange real Power and Power Losses have also been addressed in STATCOM against SVC control models. In addition to that, STATCOM-Controller’s pragmatic response has been identified and determined reliability level to maintain full capacitive output current at low system voltage. Therefore, it indicates that STATCOM device has more effectiveness than the SVC in improving transient stability (first swing).

A partial soft-switching SiC-based ANPC single-phase inverter with loss model-based dead time optimization for grid-tied PV systems

Single-phase string inverter has been widely applied to grid-tied photovoltaic (PV) rooftop applications for its renewable energy. However, the inherent attribute of intermittency in solar energy may induce instability and unqualified power. To meet the grid-interconnection standards, high demands of efficiency and harmonic distortion need to be imposed on DC/AC inverters. Conventional soft-switching inverters used to sacrificing auxiliary resonant circuits to exchange for soft switching. This requires additional costs as well as sufficient dead time to discharge junction capacitances of all switches, which exacerbates total harmonics distortion (THD) induced by dead-time effect. To improve, this paper proposes a partial soft-switching silicon carbide (SiC) -based active neutral-point-clamped (ANPC) inverter, which possesses high efficiency, eligible dead time, and no auxiliaries. 650-V SiC MOSFET is adopted for its smaller output capacitance compared with Si device. Hybrid PWM modulation is utilized to achieve partial soft switching. Whereas, the soft switching realization range and power losses highly depend on the dead time. To achieve less power loss and improved dead time effect, this paper proposes a loss model-based dead time algorithm through a Power Loss VS. Dead Time mathematical loss model. Moreover, the mechanism of the dead time affected by soft switching is explored. The transition modes, dead time configurable boundaries, and design procedure are also analyzed in detail. A 1-kW prototype is demonstrated with the input of 800 V and the rated output of 220 V/ 4.5 A. Its efficiency could reach 99.6% with THD=0.95% at full power level.

Performance analysis of a bridgeless power factor correction (PFC) buck–boost LED driver with ripple diversion scheme for extended lifespan

SummaryIn the state of the art of AC‐fed light‐emitting diode (LED) drivers, power factor correction (PFC), second harmonic LED current ripple elimination, low current total harmonic distortion (iTHD), removal of electrolytic capacitors (EC) and flicker‐free operation are the major challenging issues. This paper proposes a bridgeless universal voltagerange AC‐fed LED driver that overcome the major issues of LED driver. The bridgeless buck–boost PFC configuration minimizes the losses relative to the front‐end bridge rectifier‐based configurations. Operating in discontinuous conduction mode (DCM), the source current tracks the input voltage shape for a wide operating range, achieves inherent PFC and maintains low input current THD. Also, this provides significant reduction in the output current ripple with the ripple diversion circuit (RDC) connected in shunt across the LED load, which relatively reduces and utilizes low value of output capacitance. Hence, a flicker‐free operation is achieved without the use of electrolytic capacitors. In addition, the elimination of ECs improves the operating lifespan of the proposed LED driver. A detailed theoretical analysis and results of the proposed LED driver are validated on DSP and analog controller platforms with a 62 W/62 V experimental laboratory prototype. The experimental results confirm that the proposed LED driver achieves a power factor of 0.94–0.997, input current THD of maximum 6.8%, output current ripple of 5%, and a peak efficiency of 91.25% for the wide range of input voltage variation. These indices also satisfy IEC‐61000‐3‐2 and IEEE 1789‐2015 standard limits.

On-Chip Characterization of Ultra-Low Voltage Standard Cell Library Considering Input Slew and Output Capacitance

On-Chip Characterization of Ultra-Low Voltage Standard Cell Library Considering Input Slew and Output Capacitance

A Self-Body-Biasing Network of Vector Sum Phase Shifter for Reduction of Output Capacitance Variation and Supply Current Variation

A Self-Body-Biasing Network of Vector Sum Phase Shifter for Reduction of Output Capacitance Variation and Supply Current Variation

METHOD OF MEASURING PSRR FOR LINEAR VOLTAGE REGULATORS

The article describes a method for measuring the power supply rejection ratio and its characteristics. A simulation of the measurement in the LTspice program considering a linear voltage regulator as an example, with varying output capacitance is studied.

A Hardware-Simplified Soft-Start Scheme for Current-Fed Full-Bridge DC-DC Converter

At present, the current-fed full-bridge DC-DC converter still faces two inherent defects, namely, the soft-start issue during the start-up process and the voltage spike issue in normal working conditions. In existing research, a large number of attempts have been reported to overcome these two inherent issues. However, the existing solutions are all based on both redundant soft-start circuits and snubber circuits, and two different circuits are required. As a result, the cost of the current-fed full-bridge DC-DC converter is high, especially because the soft-start circuits are only used during the start-up process. So, to reduce device redundancy, a hardware-simplified soft-start scheme is proposed in this paper. In the proposed scheme, the snubber circuit is reused for the soft-start process based on topology reconfiguration, avoiding additional soft-start circuits to reduce the cost of this DC-DC converter. In this proposed method, the current-fed full-bridge DC-DC converter is operated as the voltage-fed full-bridge DC-DC converter by always turning on the snubber switch during the start-up process. Then, the output capacitor can be charged by slowly increasing the output voltage of the H bridge. Then, when the output voltage is high enough, the current-fed full-bridge DC-DC converter is again operated in the current-fed mode to boost the voltage. Subsequently, the converter characters and control strategy were examined and analyzed. The experimental results verify the feasibility of the proposed hardware-simplified soft-start scheme for the current-fed full-bridge DC-DC converter.

LIFETIME PREDICTION OF SINGLE-STAGE LED DRIVER CIRCUIT USING BAYESIAN BELIEF NETWORK

In light-emitting diode (LED) lighting, the driver commands the lifetime and the LED bulb. It is essential to predict the driver's lifetime during its design stage. This paper proposes a viable method to predict the lifetime of the LED driver based on its failure rate. A novel single-ended primary inductor converter (SEPIC) integrated parallel ripple cancellation circuit (PRC) topology of 30 W is considered to estimate the lifetime of the driver circuit. The failure rate model is regarded as a base to predict the lifetime of LED drivers using Bayesian belief network (BBN) analysis. The weakest links are the prime components to estimate the lifetime, and they are active devices and capacitors employed in the driver circuit. The output capacitor is considered a degree of importance as per the existing literature, and the proposed course has been designed without using any electrolytic capacitor (EC) to enhance the reliability of the driver circuit. This approach ensures an effective way to access the mean time to failure (MTTF) or the lifetime of the LED driver in a lucrative manner.

A high-load current low-dropout regulator with adaptive ESR compensation

This paper presents a dynamic pseudo equivalent series resistance (DPESR) zero-point compensation technology applied to high-current high-precision low-dropout (LDO) regulators. The DPESR circuit tracks the poles of the LDO output and adaptively generates zeros to improve stability. This compensation scheme allows the equivalent series resistance (ESR) of the output capacitor to be reduced to zero, enabling the use of miniaturized and low-ESR ceramic capacitors while reducing voltage peaks. In addition, a dynamic bias error amplifier (EA) is designed to improve transient response while ensuring that the LDO has adequate load and line regulation. The proposed LDO is designed and tested using the 0.18μm CMOS process. The test results demonstrated that the load and line regulations are 0.0028 mV/mA and 0.655 mV/V, respectively. When the input voltage VIN is 1.9 V, the output voltage VOUT is 1.5 V, and the load current is varied from 10 mA to 1.2 A, the undershoot and overshoot are 58 mV and 45 mV, respectively.

Analysis and Improved Behavior of a Single-Phase Transformerless PV Inverter

Transformerless inverters have an important role in the electrical energy market. The high-efficiency and reliable inverter concept is one of the most widely used inverters in single-phase photovoltaic systems because of its high efficiency, low cost, and reduced leakage ground current. However, the leakage ground current behavior depends on the power and weather conditions, which can increase the parasitic capacitance value, thus producing an increase in the leakage ground current magnitude. In this paper, it is proposed to add a passive inductive–capacitive output filter to the inverter structure in order to reduce the dependency of the leakage ground current on the system power and weather conditions. The inductive–capacitive output filter is designed in such a way that it can provide a low impedance path for the leakage ground current, different from the ground path. The proposed system was evaluated both through simulations and experimentally in a 1 kW laboratory prototype.

Advancing Renewable Energy: An Experimental Study of a Switched-Inductor, Switched-Capacitor Luo Boost Converter for Low-Voltage Applications

Photovoltaic (PV), battery, and fuel cell (FC) technologies are emerging forms of renewable energy gaining popularity. However, one of the key limitations is their production of direct current (DC) voltage, which hinders the connectivity and integration with the electrical grid. To address this issue, various DC/DC boost converters have been introduced. This study presents an innovative Luo converter with a switched-inductor–capacitor (SLC) cell at the input and a switched-capacitor (SC) cell at the output. The SLC cell not only increases the input voltage, but also enhances the source’s lifespan and reliability. The SC cell further amplifies the voltage, especially for high-gain applications. The proposed converter simplifies control processes by using a single power switch, significantly boosting the input voltage by 21 times with a duty ratio of 0.8. This surpasses the gains achieved by conventional boost converters by over fourfold and Luo converters by sevenfold. The second challenge when a converter is connected to these voltage sources is the potential reduction in the lifespan of the sources and the overall system due to large input current ripples. The proposed converter addresses this issue by incorporating a switched-capacitor cell on the input side. This cell charges the inductors in parallel and discharges them in series, reducing the magnitude of the input current. Another advantage of the proposed converter is its simplicity, as it employs only one power switch, minimizing the complexity of the controller system. Additionally, the distribution of the output voltage passing through the diodes between the switch and output capacitor helps mitigate voltage stress for all semiconductor devices and capacitors. The study includes thorough mathematical analyses, simulations, and laboratory tests to validate the research’s theoretical foundations.