Order Input Intercept Point Research Articles

Frequency tunable magnetostatic wave filters with zero static power magnetic biasing circuitry

A single tunable filter simplifies complexity, reduces insertion loss, and minimizes size compared to frequency switchable filter banks commonly used for radio frequency (RF) band selection. Magnetostatic wave (MSW) filters stand out for their wide, continuous frequency tuning and high-quality factor. However, MSW filters employing electromagnets for tuning consume excessive power and space, unsuitable for consumer wireless applications. Here, we demonstrate miniature and high selectivity MSW tunable filters with zero static power consumption, occupying less than 2 cc. The center frequency is continuously tunable from 3.4 GHz to 11.1 GHz via current pulses of sub-millisecond duration applied to a small and nonvolatile magnetic bias assembly. This assembly is limited in the area over which it can achieve a large and uniform magnetic field, necessitating filters realized from small resonant cavities micromachined in thin films of Yttrium Iron Garnet. Filter insertion loss of 3.2 dB to 5.1 dB and out-of-band third order input intercept point greater than 41 dBm are achieved. The filter’s broad frequency range, compact size, low insertion loss, high out-of-band linearity, and zero static power consumption are essential for protecting RF transceivers from interference, thus facilitating their use in mobile applications like IoT and 6 G networks.

Low Power RF Low Noise Amplifier Design for 5G Wi-Fi Receiver

This paper presents the design of a differential Low Noise Amplifier (LNA) for a 5th generation Wi-Fi Receiver. The circuit is implemented with 90nm transistors using CMOS technology. The proposed differential LNA for 5G Wi-Fi (IEEE 802.11ac) is designed by combining two single-ended 5G Wi-Fi LNAs with optimized design values. The gate and source degenerated inductance values are optimized to achieve a 5GHz frequency of operation. Noise neutralization capacitors of 10pF are used to reduce the channel noise in the MOSFETs used in the circuit. The differential LNA achieves 93.6% input matching, an input impedance of 45.94Ω, a transducer gain of 25.76dB, a noise figure of 1.52dB, P1dB of -11.7dBm and IIP3 of 3.17dBm. Index Terms: CMOS, Noise Figure, 1dB compression point (P1dB), Third Order Input Intercept Point (II3), harmonic signal, ISM Band

Predicting the Performance of a 26 GHz Transconductance Modulated Downconversion Mixer as a Function of LO Drive and DC Bias

The dependency of RF performance on the local oscillator (LO) drive amplitude and DC bias is an important topic for RF mixers, especially as carrier frequency increases and generation of RF power thus becomes more complex. The prediction of mixer performance, without initial reliance on full circuit simulations, can provide important insights. In this work, mathematical models without the prior use of circuit simulation are developed, leading to a strategy to predict the conversion gain (Gc), DC current, 1 dB input compression point (IP1dB) and third order input intercept point (IIP3) for a SiGe bipolar transistor transconductance mixer. The models show the possibility to trade-off LO RF power and DC bias to achieve a desired performance. The concepts allow a prediction of the necessary DC bias required to support a chosen LO level and desired conversion transconductance or linearity. The mathematical model results, circuit simulation results, and measured hardware results from a 26 GHz prototype of a single-ended mixer are presented and compared, showing good agreement. In a lab-measured example, LO power reduction from +10 dBm to +3 dBm resulted in only a 1 dB reduction in conversion gain, by modifying the DC bias as predicted. The peak conversion gain predicted by the models is within 2.0 dB of circuit simulation and 2.5 dB of measured PCB results. The RMS error for predicted DC current, compared to circuit simulation, is 1.9 mA or better.

Wideband ring mixer for band #1 of MB-OFDM systems in 180 nm CMOS technology

Abstract A wideband down conversion ring mixer is proposed for multi band orthogonal frequency division multiplexing (MB-OFDM) system in 180 nm CMOS technology. The mixer is essentially used in a heterodyne wireless receiver to enhance the selectivity of the system. Being a nonlinear system, the mixer dominates the overall performance of the system. The design of down conversion mixer is the most challenging part of a receive chain. Wideband impedance matching always remains a challenge in any radio frequency integrated circuit design. This paper presents the design of a ring mixer with high linearity, wideband impedance matching using differential resistive impedance matching and without using any DC bias. The proposed mixer is tuned for a frequency of 3.432 GHz of band 1 of the MB-OFDM system. Mixer core is based on the FET ring mixer topology. The mixer is implemented in 180 nm CMOS technology. The mixer achieves the minimum conversion loss of 10.49 dB, 1 dB compression point (P1) of 12.40 dBm, third order input intercept point (IIP3) of 12.01 dBm, a minimum SSB noise figure of 8.99 dB, and S 11 of less than -10 dB over the frequency range of 0 to 13.61 GHz . The layout of the mixer records an active area of 183.75 μm 2 .

Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

The paper presents the investigation of linearity distortion analysis of double gate junctionless transistor with high-k gate dielectrics and gate metals. As double gate junctionless transistors have shown high performance in digital circuits, linearity analysis is carried out to understand nonlinear behavior of the device for RFIC applications. In order to ensure minimum intermodulation and higher order harmonics at the system output, different linearity parameters like Second Order Voltage Intercept Point, Third Order distortion, Third Order Input Intercept Point and Third Order Intermodulation Distortion are evaluated. The results show that junctionless transistor should be biased at appropriate low voltage to ensure better linearity which is desired for RFICs. The effects of high-k gate dielectrics and gate metals on linearity characteristics of junctionless transistor are also investigated. Deterioration of the linearity is observed in junctionless transistor for the use of high-k insulators as gate dielectrics. It is also observed that low work function gate material is suitable to achieve higher linearity in low power applications.

Analysis and Design of Harmonic Rejection Low Noise Amplifier with an Embedded Notch Filter

This paper presents the analysis and design of the harmonic rejection (HR) low-noise amplifier (LNA) with the fully passive source degeneration notch filter. The proposed HR LNA provides the rejection for the strong harmonics ( 3 r d ) of the local oscillator (LO) frequencies, where the HR mixer does not provide sufficient HR performance. The proposed 3 r d harmonic notch filter modulates the source degeneration factor and the impedance matching performance thereafter. This effect further helps the blocking of the harmonic signal. The proposed LNA provides 11 dB gain at the fundamental frequency (2.1 GHz) while rejecting the 3rd harmonic component by 37 dBc. Compared to the conventional LNA, the 3rd harmonic notch performance is improved by 23 dB. Additionally, the LNA achieves a minimum noise figure of 3.1 dB, third order input intercept point ( I I P 3 ) of 0.5 dBm, input reflection (S 11 ) below −10 dB from 1.8 GHz–2.3 GHz operational frequency range, and consumed 19 mW of power from a 1.2 V supply.

Highly linear inductorless asymmetric capacitive cross-coupled wideband balun-LNAs

Two Inductorless balun low noise amplifiers (LNAs- LNA1, LNA2) are proposed in this paper to reduce the noise figure (NF) and improve the linearity. They use asymmetric capacitive cross-coupling (A-CCC) and auxiliary CS amplifier to reduce the NF. Robust derivative superposition is used in LNA2 to improve the 3rd order input intercept point, and hence the linearity. The proposed A-CCC balun-LNAs are implemented in 0.18 µm CMOS technology, and their performances are evaluated through post-layout simulations, PVT variation analysis and Monte Carlo simulations. From these studies, the average NF, gain and the 3dB-bandwidths of LNA1 and LNA2 obtained are (2.49 dB, 20 dB, 0.1–2.48 GHz) and (2.61 dB, 19.8 dB, 0.1–2.0 GHz) respectively. For a 1.2 V supply and an area of 0.02mm2, the power consumption of LNA1 and LNA2 are 4.9 mW and 5.8 mW, respectively. The performances of the proposed LNAs are also compared with other wideband LNAs reported in the literature.

Analog/RF and Linearity Distortion Analysis of MgZnO/CdZnO Quadruple-Gate Field Effect Transistor (QG-FET)

In this study, the authors propose a novel MgZnO/CdZnO Quadruple-Gate Field Effect Transistor (QG-FET). The analog/RF and linearity distortion performance of the proposed QG-FET has been analysed and compared with conventional AlGaN/GaN QG-FET having identical physical dimensions. The performance parameters including drain current (IDS), gate capacitance (Cgs), output-conductance (gd), transconductance (gm1), transconductance generation factor (TGF), intrinsic-gain (dB), cut-off frequency (fT), transconductance frequency product (TFP), first and second order derivatives of gm1 (i.e., gm2 and gm3), third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3) have been calculated. The consequences of variations in physical parameters of proposed QG-FET viz., thickness of oxide layer (tox), channel length (CL), and doping concentration (Nd) on the analog/RF and linearity distortion parameters are analyzed and compared with conventional AlGaN/GaN QG-FET. It has been revealed that MgZnO/CdZnO QG-FET yields higher IDS, gm1, TGF, intrinsic gain (dB), fT, and TFP than conventional AlGaN/GaN QG-FET with respect to different values of tox, CL, and Nd.

Linearity Distortion Analysis of III–V and Si Quadruple Gate Field Effect Transistor (QG-FET) for Analog Applications

In this work, analog and linearity distortion performance of a III–V AlGaN/GaN quadruple gate field effect transistor (III–V QG-FET) has been analyzed and compared with conventional Si QG-FET having identical physical dimensions. Specifically, we investigate the linearity by numerically computing transconductance (gm1), its second and third order derivatives (gm2 and gm3), along-with linearity metrics comprising of third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3). The consequences of variations in physical parameters of III–V QG-FET, i.e., channel length, channel height, the thickness of oxide layer, doping concentration, along-with temperature on the linearity metrics parameters, drain current, and threshold voltage are analyzed and compared with Si QG-FET. The gate capacitance and dynamic power dissipation is calculated numerically and compared by performing small signal AC analysis at 1 MHz frequency for III–V and Si QG-FETs. The influence of variations in above mentioned physical parameters is also analyzed on dynamic power dissipation and gate capacitance considering the effects of quantum capacitance in the nanometer regime. The present analysis reveals that in III–V QG-FET, the dynamic power dissipation is considerably reduced than its contender Si QG-FET due to its reduced threshold voltage, and thus it is a more promising candidate for analog and low power dissipation applications.

A Wideband Subharmonic Mixer Incorporating Signal Interference Technique Based Isolation Circuit

A broadband (8.7 GHz – 11.5 GHz) performing passive sub-harmonic down-conversion mixer using signal interference technique (SIT) is demonstrated, designed and reported in this paper. The local oscillator (LO) frequency is half of the radio frequency (RF) for the 2xsub-harmonic mixer architecture; therefore, for the RF lying in the range 8.7 GHz to 11.5 GHz, required LO frequency range is 4.25 GHz to 5.65 GHz with 0.2 GHz fixed intermediate frequency (IF). With a broadband operation, designed prototype shows single sideband down-conversion loss in the range 9.6 dB – 12.6 dB. Moreover, large-signal testing infers an adequate linear trait of the proposed design, showing -3 dBm and 11.32 dBm for the 1 dB compression point and third order input intercept point, respectively.

DTMOS based Gilbert mixer design for MICS receiver using current source helpers and switched biasing technique

In this paper, dynamic threshold MOSFET (DTMOS) based down conversion Gilbert mixer is proposed for medical implant communication services (MICS) receiver design using UMC 180 nm CMOS process. The current source helpers and switched biasing technique are used to progress the performance of the DTMOS based Gilbert mixer. The proposed design operates at a radio frequency (RF) of 403 MHz with a maximum conversion gain of 12.5 dB at 5 dBm of LO power. The 1 dB compression point and third order input intercept point (IIP3) for the proposed design is − 8.79 dBm and 3.92 dBm respectively, with a noise figure (NF) of 6.6 dB at an intermediate frequency (IF) of 10 MHz. This design circuit works in 0.9 V supply voltage and consumes a dc power of 0.55 mW with the chip area of 0.035 × 0.037 mm2. So, this design with high conversion gain and better noise performance is a suitable block for MICS applications.

A High Gain Low Noise Figure Double Balanced Down Conversion Mixer for Band 1 of WiMedia System

Objective: To propose an improved double balanced down conversion mixer for band 1 of WiMedia system at RF frequency of 3.432 GHz and IF frequency of 264 MHz. Method/Analysis: The proposed mixer is based on the Gilbert cell architecture. It uses switch bias technique to improve the noise figure and resistive current injection technique to improve the conversion gain and linearity. A resonating inductor is used to cancel out the effects of parasitic capacitances. Moreover, T type impedance matching, LC impedance matching and output buffer are used at RF trans conductance stage, LO switching stage and load stage respectively for matching purpose. Mixer is simulated in 0.18 μm CMOS technology using keysight Advanced Design System (ADS) software. Findings: Simulation results show that mixer achieves maximum conversion gain of 8.057 dB, third order Input Intercept Point (IIP3) of -10.88 dBm, Double Sideband (DSB) noise figure of 3.515 dB and S11 of -22.926 dB at 1.8 V dc supply voltage. Novelty/Improvement: A high gain, low noise figure double balanced down conversion mixer with low value of input reflection coefficient and suitable linearity is proposed for band 1 of Wimedia system. Keywords: Current Injection Technique, Double Balanced, Down Conversion Mixer, L and T Type Matching Networks, Switch Bias Technique, Wimedia System

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.

Pre‐low noise amplifier (LNA) filtering linearisation method for low‐power ultra‐wideband complementary metal oxide semiconductor LNA

This study describes the use of a pre-low noise amplifier (LNA) third-order notch filter as a novel linearity enhancement technique for ultra-wideband complementary metal oxide semiconductor LNA current-reuse topology. The second/third order input intercept point (IIP2/3) has improved along the entire working bandwidth (BW) from 2.1 to 12.5 GHz. The suggested linearisation technique achieves maximum/minimum IIP2 improvement from 19.068 to 104.143 dBm at 6.4 GHz and from 22.5 to 57.42 dBm at 5.5 GHz, respectively. In addition, this work achieves maximum/minimum IIP3 improvement from −7.956 to 34.688 dBm at 6.4 GHz and from −9.986 to 8.281 dBm, respectively. Moreover, the suggested linearisation technique does not affect the total ultra-wideband (UWB)-LNA power consumption, which is only 6.7 mW. Furthermore, the linearised UWB-LNA average noise figure is 1.6535 dB at the entire working BW. The simulation is performed and optimised with an advanced design system utilising BSIM3v3 TSMC 180 nm model files at different temperature values.

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain $$\hbox {S}_{21}$$ of $$20.10 \pm 1.65\,\hbox {dB}$$ across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, $$\hbox {S}_{11}$$ , lies below $$-\,10$$ dB from 4.9–9.1 GHz frequency. Moreover, the output reflection ( $$\hbox {S}_{22}$$ ) and reverse isolation ( $$\hbox {S}_{12}$$ ), is below $$-\,10$$ and $$-\,48$$ dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure ( $$\hbox {NF}_{min}$$ ) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of $$\pm \,0.45\,\hbox {dB}$$ in its $$\hbox {NF}_{min}$$ characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is $$-\,4.22$$ dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of $$\pm \,115\,\hbox {ps}$$ and $$\pm \,1.65\,\hbox {dB}$$ , respectively.

A Highly Linear Wide-Band Tunable Lna for Military Radio Applications

A wide-band tunable Low-Noise Amplifier (LNA) was designed to be used in military radios. The LNA works in the frequency range of 30–512 MHz where military walkie-talkies operate. To cover the wide range of operating frequencies, the output of amplifier is divided into four sub-bands with four separate external inductors and integrated capacitor arrays. The first part of the study analyzes the performance parameters such as the gain, tuning, matching, noise figure, and distortion. Layout of the design was completed, and post-layout simulations, including the layout parasitic effects, were run to quantify the performance. The LNA achieves a minimum of 12-dB gain across the entire operating frequency range. The minimum rejections achieved by the LNA at 10% and 20% offset from the center-tuned frequency were 7 dB and 13 dB, respectively. The LNA achieves a worst-case noise figure of 4.6 dB, and the impedance-match parameter (S11) is better than −20 dB under all the conditions. The worst cases P1dB (1-dB Compression Point) and IIP3 (3rd Order Input Intercept Point) were 9.1 dBm and 18 dBm, respectively, across frequency and process–voltage–temperature corners. The design dissipates 20 mA from a 3.3-V power supply and uses a 1.5-V power supply for capacitor array termination.

CMOS Front-End of LNA for GPS and GSM wireless applications

This paper describes a layout of a CMOS Low Noise Amplifier for reconfigurable packages which include GPS, GSM Wi-Fi applications. The improvement of a notably linear Radio front-stop, able to function with Galileo and GPS satellite signals suitable for coexisting in a mobile opposed environment for area based offerings, pleasing the fundamental necessities for a mass market product which includes low cost, low footprint, good accuracy, low strength intake and high sensitivity. primarily based on a wideband enter matching, the LNA stages cowl all band of hobby even as reaching a great change-off between excessive gain, low noise parent and coffee electricity intake. The complete simulation analysis of the circuit results in the frequency range of 1.4 GHz to 2 GHz. The noise figure is 1.8 dB at 1.4GHz and rises to 3.4 dB at 2 GHz. The input return and output return losses (S11, S22) of the LNA at a frequency range between 1.4 GHz and 2 GHz are S11= -12 dB, S22 =-44.73 dB at 1.77 GHz and S22 =-26.47 dB at 2 GHz. The overall gain of the LNA (S21) is 13 dB at 1.4025 GHz, 3rd order input intercept point (IIP3) = -3.16 dBm and -1dB compression point is -12.56 dBm. Input Impedance of 50Ω, 3dB Power Bandwidth of 450MHz, and Power Dissipation of 2.7mW at 1.2V power supply.

Performance characterization of USRPs

This paper presents transmitter and receiver characterization and calibration results for software defined radio systems designed using the combination of RF front end hardware like USRPs (from Ettus Research) and software interfaces like GNU Radio. The main motivation for this study was the lack of useful references pertaining to calibration of such SDR systems, confining them to proof of concept experimentation. Measurements were taken using an SDR system designed using the USRP N210 with WBX daughterboard, GNU Radio utilities, and laboratory instruments. The main aim was to determine the differences between the values obtained on the GNU Radio spectrum analyzer software GUI utility and a laboratory spectrum analyzer. One-dB compression point, third order Input Intercept point and transmitted power variation with gain were measured to determine calibration factors and offsets. Experiments were conducted over sample set of USRP N210 devices to get standardized values. The calibration factors thus obtained were used in indoor path-loss modeling and position location estimation using the CORNET nodes at Virginia Tech to determine their effectiveness. As expected the root mean square deviations from expected values were lower when calibration factors were used to correct the power measurement readings from the GNU Radio utilities.

A 0.9 V, 4.57 mW UWB LNA with Improved Gain and Low Power Consumption for 3.1–10.6 GHz Ultra-Wide Band Applications

In this paper, we present a 0.9 V, 4.57 mW UWB LNA with improved gain and low power consumption for 3.1–10.6 GHz ultra-wide band applications. In its input stage, a common gate amplifier is used to achieve approximately $$50\,\Omega$$ input resistance across the entire band, instead of using a common source stage. However, the current reused technique is used to save power consumption by using the same DC current path for both transistors in the designed circuit instead of utilizing two stage cascade configuration. The output matching is achieved by tuning the total parasitic capacitance with the inductor $$\hbox {L}_{d1}$$ at the output node. In its inter stage, inter stage matching technique is used to make the flat gain response and to extend the bandwidth, simultaneously. From simulation results, the designed LNA shows an average power gain $$\hbox {S}_{21}$$ of 15.8 dB with the gain variation of $$\pm 0.97 \hbox { dB}$$ , an input return loss $$\hbox {S}_{11}$$ of −30 to −10 dB, a high reverse isolation $$\hbox {S}_{12}$$ of −59 to −43 dB, output return loss $$\hbox {S}_{22}$$ of −16 to −10 dB, and a small group-delay variation of $$\pm 34$$ ps across the entire band. It also shows minimum achievable noise figure below 3.2 dB, and a power consumption of 4.57 mW from a supply voltage of 0.9 V. When a two tone test is performed at 8 GHz with 10 MHz spacing, the linearity of the designed LNA such as 1-dB compression point and third order input intercept point are −22.5 and −9 dBm, respectively.

Improving HRR in 3P–8P harmonic rejection mixer using modified input transconductance stage in hard switching mixer

This Paper focuses on improving the Harmonic Rejection Ratio (HRR) and the linearity of 3-Path 8-Phase harmonic rejection mixer with modified transconductance stage. The mixer core incorporates a feed-forward compensation technique in the transconductance stage for improving the linearity of the mixer with an Third order Input Intercept Point (IIP3) of 14 dBm. The Harmonic Rejection Mixer (HRM) using mixer cores with modified transconductance stage was designed using 90 nm CMOS process technology and the simulation results shows an improvement of IIP3 point of more than 25 dBm. A conversion gain of 12---4 dB was observed over the frequency range of 2.26---2.8 GHz (540 MHz bandwidth). Maximum third order HRR ($$HRR_3$$HRR3) of 45 dB and fifth order HRR ($$HRR_5$$HRR5) of 55 dB was observed on sweeping the RF power from ?30 to 10 dBm. Deviations on the performance of the HRM was found to be very minimal on PVT variation.