Optoelectronic Multichip Modules Research Articles

Optimization of Diffraction Efficiency and Polarization Dependence Loss in Photopolymer Grating for Use in Multichip Module

We in this paper propose a model to increase the diffraction efficiency of a holographic grating at 1550 nm for multiplexing application. To use such a grating, polarization dependence loss is introduced analytically and then optimized for its minimum value A configuration of holographic grating is proposed based on both maximum diffraction efficiency and minimum polarization dependence loss. The proposed grating is expected to find importance in optoelectronic multichip module.

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

3D Hybrid Integration Technology for Opto-Electronic Hetero-Integrated Systems

We developed a 3D hybrid integration technology of complementary metal oxide semiconductor (CMOS), micro electro mechanical systems (MEMS) and photonic circuits for opto-electronic hetero-integrated systems. The 3D opto-electronic multi-chip module comprising CMOS, MEMS, and photonic devices was fabricated by using 3D hybrid integration technology. The electrical chips of amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS were mounted on the electrical Si interposer with Cu through silicon vias (TSVs). The photonic chips of vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) were embedded into the optical Si interposer with an optical waveguide. The electrical and the optical interposers were precisely bonded together to form 3D opto-electronic multi-chip module. The photonics and electrical devices are communicated via Cu TSVs. The photonic devices were connected via an optical waveguide. Basic functions of CMOS, MEMS and photonic devices in the 3D opto-electronic multi-chip module were successfully evaluated.

Effect of Viscosity of Liquid Resin on Resin Self-Alignment Capability

We developed highly precise self-alignment process using resin materials for next generation microelectromechanical systems (MEMS), micro-opto-electro-mechanical systems (MOEMS) and optoelectronic multichip modules (OE-MCMs) applications. Although liquid resins have a characteristic as low as one tenth of the surface tension of solder in general, self-alignment capability could be achieved by using 3-D pads for positioning boundary. In this research, we propose the novel passive alignment mechanism in order to enhance understanding of alignment motion. Moreover, the influence of viscosity on alignment motion and alignment accuracy is demonstrated by scaled-up experiment. We could achieve highly precise alignment accuracy less than 0.4 μm.

Integrated optoelectronic transmitter and receiver multi-chip modules for three-dimensional chip-level micro-optical interconnects

We demonstrate a chip-scale micro-optical interconnect. The prototype system for this demonstration consists of optoelectronic transmitter and receiver multichip modules. A diffractive optical element (DOE) is used for optically interconnecting the multichip modules and in establishing a point-to-point link. The link length, as measured from the optical source of the transmitter to the detector plane of the receiver, is only 2.332 mm. The transmitter and receiver module dimensions as well as the integrated system volume are comparable to very large scale integration (VLSI). The design, fabrication, integration of this system, and experimental results are presented.

Optoelectronic multichip module packaging technologies and optical input/output interface chip-level packages for the next generation of hardware systems

Optical interface multichip module (MCMs) and optical interface ball grid array (BGA) packages promise to overcome the bottleneck of electrical interconnection. This will lead to telecommunications systems that have throughput exceeding several terabits per second and computer systems having speeds of several gigahertz. A national project has resulted in the development of over-100-Gb/s optoelectronic MCM (OE-MCM) packaging technologies, which will play a key role in the construction of terabits per second hardware systems. The packaging technologies feature a 10-cm square OE integrated substrate containing low-loss optical waveguides and filled vias formed by laser drilling and electroplating for improved heat dissipation, which allow higher device densities. Reliable and stable flip-chip device packaging has also been developed. This packaging features accurate photonic device bonding by microsolder bumps, low loss optical coupling using reflection mirrors, and an optical underfill technique to reduce optical reflection noise. Optical interface BGA packages using microlenses for optical input or output terminals allow high-density board packaging because of the fiberless optical interface and wide misalignment tolerances of /spl plusmn/100 /spl mu/m, which is compatible with current electronic assembly techniques. It is expected that the BGA packages will be widely developed for high-density low-cost packaging on boards.

Optoelectronic multichip module integration for chip level optical interconnects

We have integrated an 850-nm vertical-cavity surface-emitting laser (VCSEL), its driver, and a diffractive lenslet array onto a single substrate to produce an integrated optoelectronic multichip module for signal fan-out and distribution. The diffractive element performs optical fan-out of the output beam from the VCSEL into an array of focused spots at a plane 1, 416 μm from the surface of the VCSEL. This corresponds to 160 μm from the surface of the diffractive lens. System design, fabrication, integration, and experimental characterization is presented.

A siloxane polymer lightwave circuit on ceramic substrate applicable to ultrafast optoelectronic multi-chip-modules

Technique for integrating optical waveguide circuits on electrical circuits is developed toward the application to opto-electronic multi-chip modules (O/E-MCM), which enables one to handle ultrafast lightwave pulses and electrical signals on a common circuit board. We use ceramic material as the substrate of O/E-MCM having a multi-layer structure. A siloxane polymer is utilized to form low loss optical waveguides on ceramic substrates by low temperature processes. The waveguide has shown high transparency around 1310 nm. The group velocity dispersion has been measured and shown to become almost zero at wavelength of 1310 nm and about 0.4 fs/cm nm at 1550 nm. An optical circuit has been formed on simple electrical circuit consisting of a thermometer film resistance layer. A Mach–Zehnder interferometer optical switch exhibiting the waveguide extinction ratio of 30 dB, control power of 5 mW, and switching speed of 6 ms has been demonstrated. Thermal management characteristics also have been demonstrated successfully. This single-mode optical waveguide can thus be formed readily on ceramic substrates involving electrical circuit layers; this result confirms its applicability to O/E-MCM.

Advanced flip chip bonding techniques using transferred microsolder bumps

For future high-speed and high-density opto-electronic multi-chip module (OE-MCM) packaging, we developed two advanced transferred microsolder bump bonding techniques. One uses 80% Au-Sn, which allows module packaging using processes at various temperatures because it has a higher melting temperature than 100% In and 60% Sn-Pb solders. The other uses multiple transfers of bumps to achieve accurate three-dimensional flip-chip bonding with precise vertical and horizontal alignments within an error of /spl plusmn/0.5 /spl mu/m. These techniques will thus be very useful in developing high-speed and high-density OE-MCM's for multi-functional board-level interconnection in future optical communication systems.

A Study of Group Velocity Dispersion of Single-Mode Optical Waveguide Utilizing Siloxane Polymer

ABSTRACTWe have developed a single-mode optical waveguide utilizing siloxane polymer on ceramic substrate for opto-electronic multichip modules (O/E-MCM) to operate Tera bps. In this paper, we describe group velocity dispersion for the optical waveguide utilizing siloxane polymer on ceramic substrate. The group velocity dispersion becomes 0 fs/cm·nm at around 1310 nm and 1530 nm wavelength. There is abnormal dispersion at around 1530 nm. The results showed that the group velocity dispersion of the optical waveguide was significantly related to the absorption spectrum of siloxane polymer. The group velocity dispersion of the optical waveguide is about 0.4 fs/cm·nm at 1550 nm wavelength. When a 500 femto seconds optical pulse, which has 16 nm for spectrum width, pass through the 50 mm long optical waveguide, pulse expansion is estimated 20 fs/cm·nm. This expansion of spectrum is well to distinguish femto seconds optical signals. Thus, the optical waveguide utilizing siloxane polymer is capable for femto seconds optical pulses transmission.

Plastic modules for free-space optical interconnects

A combined optoelectronic and optomechanical packaging technique for the construction of snap-together free-space optical interconnect systems is described. The modules integrate relaying and routing functions by use of transparent optical molded plastic, which can achieve sufficient alignment precision that further adjustment is not required during system assembly. Methods to integrate the optoelectronic chips, such as vertical-cavity surface-emitting laser and receiver arrays with these plastic optical modules are described. Other chips can also be integrated to form optoelectronic multichip modules. These modules can also be designed to accommodate coupling to or from optical fiber arrays. A test-bed system to demonstrate the concept was assembled to a lower precision by use of conventional machining techniques.

Optimal usage of available wiring resources in diffractive–reflective optoelectronic multichip modules

Advances in VLSI and optoelectronic multichip module technologiesare enabling the construction of ultracompact massively parallelprocessing systems. The technological parameters that define thewirability and delay characteristics of these technologies have asignificant impact on the system architecture. An analytical modelis presented that allows the design space exploration of theinterconnection networks associated with multinode chips packaged on asingle multichip module substrate. Possible system designs areevaluated for a two-level interconnect with separate k-aryn-cube networks for interchip and intrachipcommunication. The impact of several architectural andtechnological parameters on the optimal network implementation (based on average no-load latency) is analyzed.

Optoelectronic multichip modules for high-speed computer systems and communication networks

The demand for communication delay and connectivity improvements suggests that optoelectronic multichip modules (OE-MCMs), utilizing photonic and electronic technologies, may provide practical solutions for high-speed interconnection problems at the module level. Design and fabrication issues for integrating optical waveguide and multiple metal layers on a single substrate are described to facilitate the practical implementation of OE-MCMs. In particular, innovative device structures and fabrication strategies are proposed such that OE-MCMs can be fabricated in a batch mode by a well-established IC fabrication process without causing any fabrication compatibility problems. The proposed OE-MCMs utilize optoelectronic interconnection, multichip module packaging, and MEMS fabrication technologies at the module level, and the feasibility of the proposed OE-MCMs has been demonstrated through the fabrication, assembly, and characterization of prototypes.

Physical models and algorithms for optoelectronic MCM layout : JIAO FAN, DAVID ZALETA, CHUNG-KUAN CHENG and SINGH H. LEE. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1), 124 (May 1995)

Physical models and algorithms for optoelectronic MCM layout : JIAO FAN, DAVID ZALETA, CHUNG-KUAN CHENG and SINGH H. LEE. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1), 124 (May 1995)

Laser-diode array packaging in opto-electronic multichip modules

An opto electronic multichip module (OE-MCM) constructed from optical polyimide waveguides on an OE substrate has been developed for high-speed, wideband communication systems. This paper describes the packaging of the laser-diode (LD) array on the OE substrate, which is composed of low-loss (0.4 dB/cm at 1.3 /spl mu/m) optical polyimide waveguides on a copper-polyimide multilayer substrate. High-speed (Gbit/s) electrical signals are transmitted through electrical lines in the copper-polyimide layers. A junction-up, five-channel InGaAsP edge-emitting LD array is aligned to the waveguides in the plane direction with an error margin of 2 /spl mu/m by using a standard surface for vertical positioning. The bottom of the LD array is connected to columnar thermal vias under the bonding area for heat dissipation. The emitted light power is considered to be stable because no kinks and good linearity are observed in the I-L characteristics of the coupled LD array. The coupling loss was estimated to be 6.5 dB with a deviation between channels of /spl plusmn/0.3 dB.

New optical and electrical hybrid packaging techniques using optical waveguides for optoelectronic multichip modules

An optoelectronic multichip module (OE-MCM) using fluorinated polyimide optical waveguides is proposed. This module can be produced with an optoelectrical substrate (OE-substrate), incorporating photodiode-to-waveguide coupling, and fiber-to-waveguide coupling. The OE-substrate is composed of fluorinated polyimide optical waveguides fabricated onto a copper-polyimide multilayer electrical substrate. Propagation loss of the optical waveguide is low at 0.4 dB/cm. There is no change in the optical characteristics of the waveguide after heat-treatment during the solder bonding process. The waveguide-to-photodiode coupling is achieved by deflecting the propagating light with a total internal reflection (TIR) mirror, and self-alignment of the photodiode is achieved using micro-solder bumps. The TIR mirror shows low reflection loss of less than 1.5 dB. The solder bumps can position the photodiode accurately within /spl plusmn/1 /spl mu/m. A fiber guiding groove is used for alignment-free coupling between inter-modules. The coupling loss between the fiber and the waveguide is estimated to be 3.2 db with the deviation of about 0.1 dB. These techniques make OE-MCM's attainable.

Design considerations and algorithms for partitioning optoelectronic multichip modules

There is considerable interest in the development of optical interconnects for multichip modules (MCM's) to improve their performance. For effective utilization of the optical and electronic technologies, a methodology for partitioning the system is required. The key question to be answered is which technology should be used for each interconnect in a given netlist: optical or electronic. We introduce the computer-aided design approach for partitioning optoelectronic systems into optoelectronic MCM's. We first discuss the design trade-off issues in an optoelectronic system design, including speed, power dissipation, area, and diffraction limits for free-space optics. We then define a formulation for optoelectronic MCM partitioning and describe new algorithms for optimizing this partitioning based on the minimization of the power dissipation. The models for the algorithms are discussed in detail, and an example of a multistage interconnect network is given. Different results, with the number and size of chips being variable, are presented in which improvement for the system packaging has been observed when the partitioning algorithms are applied.

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over "long" distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Packaging considerations for planar optical interconnection systems

We discuss various aspects of building an integrated optoelectronic system that is based on the concept of planar optics. A particular optical interconnection system has been fabricated and demonstrated. It provides parallel interconnections with 1024 optical channels that could be useful as an optical backplane in an optoelectronic multichip module. We consider the design and the fabrication of the optical system, schemes for the hybrid integration with optoelectronic device arrays, and the thermal management of an integrated system. The proposed hybrid integration scheme is based on mature technologies such as thermal anodic bonding and flip-chip bonding. Possibilities for efficient heat sinking are described.

Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects

Decreasing the system volume for optoelectronic (OE) planar systems is achieved by advancing computer-aided design of OE multichip modules (MCM's). It is shown that in order to minimize the volume in an OE MCM, it is necessary to minimize the maximum interconnect distance. To achieve this, we have developed placement algorithms based on the constraints of a given irregular interconnect pattern. Results are given for a twin-butterfly network for two general physical models: a transmissive MCM and a reflective MCM. We then show three different types of hologram design that can be used to implement the interconnect array. These elements are for reconstruction in the near field and are fabricated by direct-write electron-beam lithography. Both simulated and experimental reconstructions are demonstrated.