Optimum Source Impedance Research Articles

Impact of process parameters variation on noise and linearity performances of GC-JL-GAA MOSFET

ABSTRACT The short channel effects are improved in GC-JL-GAA MOSFETs by raising the channel’s graded doping level. The noise and linearity of the device plays a crucial role in RFIC circuit applications. Therefore, this article presents a comprehensive analysis of noise and linearity parameters of graded channel junction-less-gate-all-around (GC-JL-GAA) MOSFET with process parameter variations through 3D Silvaco ATLAS device simulator. This paper investigates the noise parameters such as Noise Conductance (NC), minimum noise figure (NFmin), and optimum source impedance (Z0). To comprehend the performance of GC-JL-GAA MOSFETs, the noise characteristics with changes in channel thickness, channel length, high-k gate oxide, and oxide thickness are examined and compared. Moreover, the effect of process parameter variation on linearity FOMs such as gm2, gm3, IIP3, IMD3, VIP2, VIP3, and 1-db compression point are also examined. The GC-JL-GAA device, however, provides improved noise and linearity performance parameters for lower channel length of the device as per the performance evaluation. Furthermore, it has been observed that high-k gate oxide deteriorates noise and linearity performance of GC-JL-GAA MOSFETs. Based on the results of the performance evaluation, it has been revealed that the GC-JL-GAA devices are suitable to be employed in Radio Frequency (RF) applications.

Design of Ku-band power amplifier for satellite applications using neural network

Power amplifier one of the most important part of a transmitter. For the proposed power amplifier, the optimum load and source impedances have been calculated by source and load-pull analysis. The device selected is Cree CGHV1J006D, and the substrate chosen is alumina. With help of neural network algorithm the optimum matching architecture design of input and output network are calculated and the value is validated through Keysight ADS. At frequency range of 13.75 GHz-14.5 GHz maximum drain efficiency of 32.434% and the gain of 4.236 dB is achieved. The proposed power amplifier(PA) have dimension of 22 mm × 4 mm. With an output power of more than 35 dBm, these results represent state-of-the-art performance in terms of power efficiency in the Ku-band.

A multi‐variable double impedance matching network design algorithm with design example of a low noise amplifier

In this article, we propose a matching network design algorithm based on the segmentation of the real and imaginary part of optimum source impedance curve with respect to space variable x $$ x $$ and frequency ω $$ \omega $$ , respectively. The impedance curve (comprising of real and imaginary parts) is approximated as a collection of n $$ n $$ linear segments, represented by the weighted sum of n $$ n $$ semi-infinite linear functions. Using the numerical method, optimum weight vectors that maximize transducer power gain are obtained to model the real and imaginary parts of the source impedance curve. We get the values of optimum weight vectors and the rational input impedance function for the matching network, which are then synthesized in the desired topology by a continued partial fraction. Experimentally, we validate the novelty of the proposed method by designing matching networks of a wideband custom monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) in 1.3–2.3 GHz frequency band. The measured results of the designed LNA are significantly close to the simulated results. We bias our LNA at (5 V, 150 mA) and achieve a maximum noise figure of 1.25 dB, OP1dB of 26 dBm, and an average TOI of 38 dBm. Moreover, our design of custom LNA MMIC has an integrated ESD structure while occupying only 0.32 mm2 of chip area.

Optimization of LNA’s first stage to reduce overall noise figure in multi-stage LNAs

An analytical approach for designing the first stage in multi-stage low noise amplifiers (LNAs) is presented. This paper discusses the first stage optimization for minimizing the overall Noise Figure (NF) with consideration of following stage’s noise. This approach focuses on source impedance optimization of first stage while considering its NF, gain and the effect of the following stage’s NF simultaneously. The proposed approach calculates the first stage’s design parameters to have minimum overall NF in a multi stage LNA while the conventional approach suggests optimum source impedance to achieve minimum NF in first stage. In this paper, it is proved that constant overall-NF contours in Smith chart are different from traditional NF circles and Γopt for best noise performance changes in multi stage LNAs with different NF in adjacent stages. These contours and the optimum source impedance are depicted for specific LNA and compared with its constant NF circles and Γopt. For checking the feasibility of proposed approach and also validation of theoretical and simulation results a discrete LNA in 4–5 GHz using ATF13136 transistor is made. Results show that considering the subsequent circuit’s noise in LNA’s first stage design reduces overall-NF while improves its gain and input matching.

Noise Wave Modeling of an SIS Mixer and Its IF Circuit Using Tucker's Quantum Theory of Mixing

Tucker's Quantum Theory of Mixing (QTM) is widely used to model the conversion gain and noise temperature of SIS mixers. In particular, the theory describes the phenomenon of non-classical conversion gain and that of infinite or even negative output impedances in inductively tuned SIS mixers. Common microwave noise theory is inadequate to describe the operation of the IF circuit connected to such mixers. In this paper, we report the use of the noise wave formalism to model the noise properties of a Double-Side-Band SIS mixer together with an IF isolator and low noise amplifier cascade. Starting from QTM, we derive the 4 noise parameters of the SIS mixer, together with an approximate 2-port chain matrix with an upper-side-band RF input port and an IF output port. These matrices are cascaded with the noise correlation matrix of the IF circuit to form a complete noise model of the SIS receiver. Optimum source impedance for the receiver can be derived from this noise model, which can be used in efficient CAD modeling of a complete SIS receiver.

S-대역 300 W급 GaN HEMT 고조파 튜닝 내부 정합 전력증폭기

Herein, an S-band internally-matched power amplifier that shows a power capability of 300 W in a Long Term Evolution(LTE) band 7 is designed and fabricated using a CGHV40320D GaN HEMT from Wolfspeed. Based on the nonlinear model, the optimum source and load impedance are extracted from the source-pull and load-pull simulations at the fundamental and harmonic frequencies, and the harmonic impedance tuning circuits are implemented inside a ceramic package. The internally matched power amplifier, which is fabricated using a thin-film substrate with a high relative permittivity of 40 and an RF35TC PCB substrate, is measured at the pulsed condition with a pulse period of 1 ms and a duty cycle of 10%. The measured results show a maximum output power of 257～323 W, a drain efficiency of 64～71%, and a power gain of 11.5～14.0 dB at 2.62～2.69 GHz. The LTE-based measurement shows a drain efficiency of 42～49% and an ACLR of less than −30 dBc(excluding 2.62 GHz) at an average power of 79 W.

Design of a 2.5‐kW L‐band solid‐state pulsed power amplifier for radar applications

A compact design for a 2.5 kW solid-state power amplifier (PA) based on 330-W laterally diffused metal–oxide semiconductor transistors over 1.2–1.4 GHz is proposed. The design procedure is started with the design and implementation of a 330-W unit amplifier (UA) independently. Optimum load and source impedances of the UA are obtained by pulling the source and load impedances with the aid of the simulator utility provided in Advanced Design System. The input–output matching networks are designed and implemented using multi-section microstrip transmission lines. In order to construct a 2.5-kW high PA (HPA), the eight pieces of designed UA are combined. A low-loss 1–8 way planar binary power divider with an 8–1 way planar binary power combiner is used to divide and combine the microwave signals through eight UAs. The HPA delivers 63.7–64.3 dBm output power with 16.7–17.3 dB power gain and 55–60.4% power-added efficiency over 1.2–1.4 GHz. To the best of the authors' knowledge, the most compact HPA design using packaged transistor at L-band with such high output power level ever reported is presented.

Method for Adjusting Single Matching Network for High-Power Transfer Efficiency of Wireless Power Transfer System

A wireless power transfer (WPT) system is generally designed with the optimum source and load impedance in order to achieve the maximum power transfer efficiency (PTE) at a specific coupling coefficient. Empirically or intuitively, however, it is well known that a high PTE can be attained by adjusting either the source or load impedance. In this paper, we estimate the maximum achievable PTE of WPT systems with the given load impedance, and propose the condition of source impedance for the maximum PTE. This condition can be reciprocally applied to the load impedance of a WPT system with the given source impedance. First, we review the transducer power gain of a two-port network as the PTE of the WPT system. Next, we derive two candidate conditions, the critical coupling and the optimum conditions, from the transducer power gain. Finally, we compare the two conditions carefully, and the results therefore indicate that the optimum condition is more suitable for a highly efficient WPT system with a given load impedance.

Noise analysis of gate electrode work function engineered recessed channel (GEWE-RC) MOSFET

This paper discusses the noise assessment, using ATLAS device simulation software, of a gate electrode work function engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the behaviour of GEWE-RC MOSFET is compared with that of a conventional MOSFET having the same device parameters. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and noise reduction is a major concern. The noise metrics taken into consideration are: minimum noise figure and optimum source impedance. The statistical tools auto correlation and cross correlation are also analysed owing to the random nature of noise.

A GPS LNA RFIC with voltage‐controlled noise and input matching

AbstractA low‐noise amplifier (LNA) design with a voltage‐controlled matching section using a transistor for optimal matching between noise figure (NF) and input impedance is proposed in this letter. A crucial goal for the design is to achieve low NF required in the global positioning systems with a good input matching. The proposed design is based on the cascade of a common‐gate and common‐source transistor. The gate voltage of a common‐gate transistor is used to control the real part of optimum source impedance (Zopt) approximates to 50 Ω for NF and input impedance matching. Because the design does not require inductors or capacitors for noise matching, it reduces NF and chip area substantially. The LNA is designed and implemented using WIN 0.15 μm PHEMT foundry process and has an area of 0.84 mm × 0.84 mm. The power consumption is 18 mW from a 2.5 V supply voltage. The measurement results of the proposed LNA RFIC are 2.4 dB NF, 12.6 dB gain; input‐referred 1 dB compression point (IP1dB) is −6 dBm, and input‐referred third‐order intercept point is 6.3 dBm. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 54:332–335, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26524

Ultralow-noise chopper amplifier with low input charge injection

A chopper amplifier is presented that achieves an ultralow voltage noise of 0.73 nV/√Hz down to a few millihertz. Excess white and 1/f current noise was observed, which increases with the chopping frequency. At the lowest chopping frequency of 570 Hz, a noise level of 40 fA/√Hz with a 1/f corner at 3 mHz is obtained, corresponding to a noise temperature around 1 K at the optimum source impedance of 18 kΩ. Special care was taken to compensate the effect of switching spikes in the input chopper, resulting in a low charge injection into the signal source. The amplifier has a fixed gain of 1000. Postamplification and postfiltering with a wide range of settings, as well as optical output isolation based on a highly linear voltage-to-frequency converter, make the instrument well suited for demanding applications in metrology.

Design and Analysis of a Cascode Bipolar Low-Noise Amplifier With Capacitive Shunt Feedback Under Power-Constraint

A cascode bipolar low-noise amplifier (LNA) with capacitive shunt feedback has been developed to present a solution for simultaneous noise and power match when the real part of the optimum source impedance is not 50 Ω in order to keep high current density under power constraint. The proposed LNA also has the capability for the simultaneous improvement of noise figure (NF) and linearity. In addition, we analyzed and verified that the second-order interaction, which affects the third-order nonlinearity, becomes less sensitive to the low-frequency input termination at higher bias currents. The possibility of removing the low-frequency LC trap is investigated based on this analysis. We also show that LNAs with smaller base and/or smaller emitter resistances require lower source impedance at low frequencies to improve linearity by the same amount. Finally, prudent layouts for improving the performance of the LNA are considered. Eleven design examples of the proposed LNA, which individually operate at 880, 1575, or 1960 MHz, are fabricated in a low-cost 0.35- μm SiGe BiCMOS process to verify the design and analysis experimentally. The fabricated LNAs have excellent performances, especially in NF. For example, the 880-MHz LNA has an NF of 0.9 dB, a power gain of 16 dB, and an IIP3 of +14 dBm with current consumption of 11 mA from a 2.8-V power supply.

Theory and Design of Low-Noise Multipath Amplifiers

The theoretical minimum noise measure of a multipath amplifier (an amplifier that has multiple parallel amplifiers) is achieved by using the optimum source impedance and optimum gain for each amplification path. This optimum source impedance and gain can be calculated by replacing each amplifier with its optimum source impedance. The resulting noise measure is the same as the minimum noise measure of the amplifiers used. The theory is demonstrated by applying it to distributed am plifiers. In an ideal distributed amplifier, the magnitude of the optimum gain of the amplification paths decreases and the phase delay increases the farther the stage is from the input, with the decrease in gain being faster for higher frequencies. The challenge in designing broadband low-noise distributed amplifiers is to achieve optimum gain matching over broad bandwidths. A numerical optimization procedure that separates source impedance and gain matching is proposed and demonstrated by optimizing a 0.5-2-GHz distributed amplifier. An average noise measure of 0.3 dB is achieved, which is only 0.1 dB higher than the minimum noise measure of the amplification stages used. This increase is due to transmission line loss and gain mismatch.

Design of a Highly Efficient 2–4-GHz Octave Bandwidth GaN-HEMT Power Amplifier

In this paper, the design, implementation, and experimental results of a high-efficiency wideband GaN-HEMT power amplifier are presented. A method based on source-pull/load-pull simulation has been used to find optimum source and load impedances across the bandwidth and then used with a systematic approach to design wideband matching networks. Large-signal measurement results show that, across 1.9-4.3 GHz, 9-11-dB power gain and 57%-72% drain efficiency are obtained while the corresponding power-added efficiency (PAE) is 50%-62%. Moreover, an output power higher than 10 W is maintained over the band. Linearized modulated measurements using a 20-MHz long-term evolution signal with 11.2-dB peak-to-average ratio show an average PAE of 27% and 25%, an adjacent channel leakage ratio of -44 and -42 dBc at 2.5 and 3.5 GHz, respectively.

Design of a Class F Power Amplifier

A Class F power amplifier (PA) at 2.5GHz has been designed and fabricated. Test results show 15.7dB gain with 75.75% power added efficiency ( PAE), at an input level of 25dBm. The design procedure is presented, with various issues illustrated and addressed. A new method is proposed to obtain the optimum load and source impedances without iterations, which would usually be necessary.

Characterization and modeling of AlGaN∕GaN heterostructure field effect transistors for low noise amplifiers

A simple equivalent circuit model including noise sources for the GaN heterostructure field effect transistor is presented and analyzed. The model is used to determine optimum source impedance for low noise amplifier applications. A good agreement between the model and measured NFmin of experimental devices is shown. Prototype transistors with a 0.75μm gate length and 80μm width delivered a power-added efficiency of 45.6% and a minimum noise figure of 2.1dB at 2.4GHz when operated from a 48V supply. Gate leakage current was found to be an important noise source.

The Effect of Geometry on the Noise Characterization of SiGe HBTs and Optimized Device Sizes for the Design of Low-Noise Amplifiers

The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 /spl Omega/. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.

리플렉터 형태의 K-대역 주파수 체배기 구현에 관한 연구

본 논문에서는 고주파 특성이 우수한 NEC사의 ne71300-N MESFET를 이용하여 24GHz 대역 국부발진기용 주파수 체배기를 설계 및 제작하였다. 멀티하모닉 로드 풀 시뮬레이션을 통하여 최적의 고조파 소스ㆍ부하 임피던스를 선택하였다. 리플렉터를 이용하여 변환 이득을 개선할 수 있었고, 대역저지필터를 이용하여 기본파와 3차 고조파 성분을 억제하였다. 측정한 결과 0 dBm의 입력신호에 대해 출력주파수인 24Ghz에서의 출력 전력은 -3.776dBm이고, 변환 이득은 0.736 dBm, 41.064 dBc의 높은 고조파 억압 특성을 얻었다. In this paper, a reflector type frequency doubler for local oscillator at 24GHz is designed and fabricated with ne71300-N MESFET. Optimum source and load impedances are decided through a multiharmonic load pull simulation technique. A conversion gain can be improved using the reflector and fundamental and third harmonics are well suppressed with open stub of <TEX>$\lambda$</TEX>/4 length Measured results show output power at 0dBm of input power is -3.776dBm, conversion gain 0.736dB, harmonic suppression 41.064dBc, respectively.

Frequency-scalable SiGe bipolar RF front-end design

The optimum collector current density, at the global minimum noise figure (NF) point for a bipolar transistor, scales linearly with frequency. The optimum source impedance, on the other hand, remains constant if the device area is scaled inversely with frequency. As a result, transforming the design from one frequency to another can be achieved by simple circuit scaling. Taking advantage of the shallow nature of the NF/sub min/ global minima, it is possible to increase the linearity of the low-noise amplifier (LNA) or decrease its power consumption, which is required for multimode designs, with little degradation in NF. These theoretical results have been applied to LNA and active mixer designs, and verified by constructing a 1.8-GHz frequency-scaled SiGe bipolar test chip. The measured LNA NF is 1.3 dB at 4.5 mA, while the double-balanced mixer achieves a single-sideband (SSB) NF of 6.1 dB for the low-linearity mode and an IIP3 and an SSB NF of +3 dBm and 6.6 dB, respectively, for the high-linearity mode.

Characterization of the Input Noise Sources of a dc SQUID

From the theory of the intrinsic noise in a dc SQUID by Tesche and Clarke, we derive the expressions of the current and voltage input noise spectral densities in a dc SQUID current amplifier operated in a flux locked mode. The expected current and voltage noises are compared, at audio frequencies, with the experimental results obtained with a low noise dc SQUID in which the input load (resonant and not) and the operating temperature (1–4 K) are changed. In order to evaluate the input voltage noise, which is directly related to the current noise around the SQUID loop and is usually neglected, we have used as the input circuit a LC resonator with a very high quality factor (≈106). Both the voltage and current input noises exceed the expected values by the same factor of about 8. This means that the modulus the optimum source impedance of the SQUID amplifier is still in agreement with the value expected from the theory, which is approximately given by the product of the input coil inductance and the angular frequency. To explain the excess noise results, we propose a model in which the voltage and current input noises are due to a thermal magnetic noise source which is present near the SQUID.