Circuit Design Optimization Research Articles

A Tunable Long Duration Pulse Generation Circuit in Mammalian Cells.

Pulse generator circuits based on incoherent feed-forward logic have been developed in bacterial, yeast, and mammalian systems but are typically limited to production of short pulses lasting less than 1 day. To generate longer-lasting pulses, we introduce a feedback-based topology that induces multiday pulsatile gene expression with tunable duration and amplitude in mammalian cells. We constructed the circuit using the PERSIST platform, which consists of entirely post-transcriptional logic, because our experience suggests that this approach may attenuate long-term epigenetic silencing. To enable external regulation of PERSIST regulatory elements, we engineered inducer-stabilized CRISPR endoRNases that respond to FDA-approved drugs, generating small molecule responses with greater than 20-fold change. These inducer-responsive proteins were connected to a two-state cross-repression positive feedback topology to generate the pulse generator circuit architecture. We then optimized circuit design through chromosomal integration of circuit components at varying stoichiometries, resulting in a small library of circuits displaying tunable pulses lasting between two and 6 days in response to a single 24 h input of inducer. We expect that the small molecule-stabilized PERSIST proteins developed will serve as valuable components in the toolbox for post-transcriptional gene circuit development and that tunable post-transcriptional pulse generator circuits in mammalian cells will enable study of endogenous hysteretic gene networks and support advances in cell therapies and organoid engineering.

Reconfigurable dielectric engineered WSe2/HZO mem-transistor

Abstract Hybrid systems coupling 2D semiconductors with functional ferroelectrics are attracting increasing attention due to their excellent electronic/optoelectronic properties and new functionalities through the multiple heterointerface interaction. In our device architecture, interfacial states are introduced on the ferroelectric Hf0.5Zr0.5O2 thin film as gate dielectric layer for charge trapping effect. Utilizing the collaborative effects of charge trapping and ferroelectric polarization behavior, a multifunctional 2D WSe2/HZO memtransistor is demonstrated with ultra-low off-state (dark) current of 10-13 A, high on/off ratio of 106 and linear conductance update. This device exhibits reliable memory properties and tunable synaptic functions including short-term plasticity (STP)/ long-term plasticity (LTP), paired pulse facilitation (PPF), spike-timing dependent plasticity (STDP), synaptic potentiation/depression, and filtering in a single device. Extensive endurance tests ensure robust stability (1000 switching cycles, 2000 s holding time) and the synaptic weight update in the device exhibits excellent linearity. Based on the experimental data, our devices eventually achieve an accuracy of 94.8% in artificial neural network simulations. These results highlight a new approach for constructing hybrid systems coupling 2D semiconductors with functional ferroelectrics in a single device for tuning synaptic weight, optimizing circuit design, and building artificial neuromorphic computing systems.

Efficient power conversion with four switch soft-switching boost integrated half-bridge dual-output series resonant converter

Soft switching reduces voltage and current stress during transitions, smoothing and quieting operations and reducing electromagnetic interference while also increasing efficiency and equipment lifespan. Circuit design, component selection, and switching frequency optimization affect power electronics soft switching. This paper proposes boost integrated half-bridge dual-output series resonant (BIHBDOSR) converter, a novel converter design and control method to increase series resonant converter performance by reducing storage element size, switch count, and switching losses. This methodology relies on soft-switching technologies like zero-voltage switching (ZVS) and zero-current switching (ZCS). These methods use class-D, class-E, series, parallel, and series–parallel resonant converter circuits to increase efficiency and minimize component stress. The proposed converter is ideal for constant voltage, constant power, and current-controlled loads with the output voltage being regulated by a closed-loop PI controller. The output voltages for two loads in the simulation depart from reference values. V01 changes from 14 to 20 V and V02 from 18 to 15 V at 300 ms owing to switching variances. The proposed converter utilizes gate driver circuits, resonant tank circuit, current sensor, FPGA board for closed-loop control, and current sensor for stability, ensuring converter stability. The proposed converter closed-loop control method modifies PWM signals to regulate both loads independently and ensure steady output voltage. Additionally, to validate the effectiveness of proposed converter, a 50-W driver circuit is designed, delivering two independent outputs of 20 W and 30 W. Frequency modulation (FM) and duty cycle control methods are employed to obtain the desired outputs.

Synergistic Dynamical Decoupling and Circuit Design for Enhanced Algorithm Performance on Near-Term Quantum Devices.

Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms.

A Review of Electromagnetics-Based Microwave Circuit Design Optimization

A Review of Electromagnetics-Based Microwave Circuit Design Optimization

Evaluation of a Simplified Modeling Approach for SEE Cross-Section Prediction: A Case Study of SEU on 6T SRAM Cells

Electrical models play a crucial role in assessing the radiation sensitivity of devices. However, since they are usually not provided for end users, it is essential to have alternative modeling approaches to optimize circuit design before irradiation tests, and to support the understanding of post-irradiation data. This work proposes a novel simplified methodology to evaluate the single-event effects (SEEs) cross-section. To validate the proposed approach, we consider the 6T SRAM cell a case study in four technological nodes. The modeling considers layout features and the doping profile, presenting ways to estimate unknown parameters. The accuracy and limitations are determined by comparing our simulations with actual experimental data. The results demonstrated a strong correlation with irradiation data, without requiring any fitting of the simulation results or access to process design kit (PDK) data. This proves that our approach is a reliable method for calculating the single-event upset (SEU) cross-section for heavy-ion irradiation.

Simulations of superconducting quantum gates by digital flux tuner for qubits

Abstract The interconnection bottleneck caused by limitations of cable number, inner space and cooling power of dilution refrigerators has been an outstanding challenge for building scalable superconducting quantum computers with the increasing number of qubits in quantum processors. To surmount such an obstacle, it is desirable to integrate qubits with quantum–classical interface (QCI) circuits based on rapid single flux quantum (RSFQ) circuits. In this work, a digital flux tuner for qubits (DFTQ) is proposed for manipulating flux of qubits as a crucial part of the interface circuit. A schematic diagram of the DFTQ is presented, consisting of a coarse tuning unit and a fine-tuning unit for providing magnetic flux with different precision to qubits. The method of using DFTQ to provide flux for gate operations is discussed from the optimization of circuit design and input signal. To verify the effectiveness of the method, simulations of a single DFTQ and quantum gates including a Z gate and an iSWAP gate with DFTQs are performed for flux-tunable transmons. The quantum process tomography corresponding to the two gates is also carried out to analyze the sources of gate error. The results of tomography show that the gate fidelities independent of the initial states of the Z gate and the iSWAP gate are 99.935% and 99.676%, respectively. With DFTQs inside, the QCI would be a powerful tool for building large-scale quantum computers.

Synthetic bacteria designed using ars operons: a promising solution for arsenic biosensing and bioremediation.

The global concern over arsenic contamination in water due to its natural occurrence and human activities has led to the development of innovative solutions for its detection and remediation. Microbial metabolism and mobilization play crucial roles in the global cycle of arsenic. Many microbial arsenic-resistance systems, especially the ars operons, prevalent in bacterial plasmids and genomes, play vital roles in arsenic resistance and are utilized as templates for designing synthetic bacteria. This review novelty focuses on the use of these tailored bacteria, engineered with ars operons, for arsenic biosensing and bioremediation. We discuss the advantages and disadvantages of using synthetic bacteria in arsenic pollution treatment. We highlight the importance of genetic circuit design, reporter development, and chassis cell optimization to improve biosensors' performance. Bacterial arsenic resistances involving several processes, such as uptake, transformation, and methylation, engineered in customized bacteria have been summarized for arsenic bioaccumulation, detoxification, and biosorption. In this review, we present recent insights on the use of synthetic bacteria designed with ars operons for developing tailored bacteria for controlling arsenic pollution, offering a promising avenue for future research and application in environmental protection.

Surpassing millisecond coherence in on chip superconducting quantum memories by optimizing materials and circuit design.

The performance of superconducting quantum circuits for quantum computing has advanced tremendously in recent decades; however, a comprehensive understanding of relaxation mechanisms does not yet exist. In this work, we utilize a multimode approach to characterizing energy losses in superconducting quantum circuits, with the goals of predicting device performance and improving coherence through materials, process, and circuit design optimization. Using this approach, we measure significant reductions in surface and bulk dielectric losses by employing a tantalum-based materials platform and annealed sapphire substrates. With this knowledge we predict the relaxation times of aluminum- and tantalum-based transmon qubits, and find that they are consistent with experimental results. We additionally optimize device geometry to maximize coherence within a coaxial tunnel architecture, and realize on-chip quantum memories with single-photon Ramsey times of 2.0 - 2.7 ms, limited by their energy relaxation times of 1.0 - 1.4 ms. These results demonstrate an advancement towards a more modular and compact coaxial circuit architecture for bosonic qubits with reproducibly high coherence.

Near-Field Probing of Microwave Oscillators with Josephson Microscopy.

Voltage-controlled oscillators, serving as fundamental components in semiconductor chips, find extensive applications in diverse modules such as phase-locked loops, clock generators, and frequency synthesizers within high-frequency integrated circuits. This study marks the first implementation of superconducting Josephson probe microscopy for near-field microwave detection on multiple voltage-controlled oscillators. Focusing on spectrum tracking, various phenomena, such as stray spectra and frequency drifts, were found under nonsteady operating states. Parasitic electromagnetic fields, originating from power supply lines and frequency divider circuits, were identified as sources of interference between units. The investigation further determined optimal working states by analyzing features of the microwave distributions. Our research not only provides insights into the optimization of circuit design and performance enhancement in oscillators but also emphasizes the significance of nondestructive near-field microwave microscopy as a pivotal tool in characterizing integrated millimeter-wave chips.

Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering.

In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, and ultimately enhance the efficiency and effectiveness of electronic circuits. This paper comprehensively reviews the application of machine learning techniques in circuit design optimization. Supervised learning algorithms such as neural networks, support vector machines, and decision trees enable the modeling of intricate interdependencies within electronic circuits. Unsupervised learning techniques, including clustering and dimensionality reduction, facilitate efficient exploration of the design landscape by identifying patterns and correlations. Additionally, reinforcement learning algorithms offer an autonomous approach to circuit optimization through iterative learning and refinement. Real-world applications of machine learning-driven optimization in electronics and computer engineering span various domains, including power-efficient integrated circuits, signal processing algorithm optimization, and layout optimization for enhanced performance and reliability. Moreover, machine learning techniques play a crucial role in mitigating variability in semiconductor manufacturing processes, ensuring robustness and reliability of electronic systems in the face of uncertainties. Despite the promising potential of machine learning in circuit design optimization, challenges such as dataset acquisition, model interpretability, and scalability to complex circuits persist. Addressing these challenges requires innovative research endeavors, including the development of hybrid optimization techniques and novel hardware architectures. DOI: https://doi.org/10.52783/tjjpt.v45.i02.6339

Modeling of Schottky diode and optimal matching circuit design for low power RF energy harvesting

This work designs and implements a single-stage rectifier-based RF energy harvesting device. This device integrates a receiving antenna and a rectifying circuit to convert ambient electromagnetic energy into useful DC power efficiently. The rectenna is carefully engineered with an optimal matching circuit, achieving high efficiency with a return loss of less than −10 dB. The design uses a practical model of the Schottky diode, where both RF and DC characteristics are derived through extensive experimental measurements. The results from both experiments and simulations confirm the effectiveness of the design, showing its proficiency in efficient RF energy harvesting under low-power conditions. The antenna produced operates in the wifi band with a gain close to 4 dBi and a bandwidth of 100 MHz. With a load resistance of 1600 Ω, the proposed device achieves an impressive RF-to-DC conversion efficiency of approximately 52% at a low incident power of −5 dBm. These findings highlight the potential and reliability of rectenna systems for practical and efficient RF energy harvesting applications. The study significantly contributes to our understanding of rectenna-based energy harvesting, providing valuable insights for future design considerations and applications in low-power RF systems.

Pareto Optimization of Analog Circuits Using Reinforcement Learning

Analog circuit optimization and design presents a unique set of challenges in the IC design process. Many applications require the designer to optimize for multiple competing objectives, which poses a crucial challenge. Motivated by these practical aspects, we propose a novel method to tackle multi-objective optimization for analog circuit design in continuous action spaces. In particular, we propose to (i) extrapolate current techniques in Multi-Objective Reinforcement Learning to continuous state and action spaces and (ii) provide for a dynamically tunable trained model to query user defined preferences in multi-objective optimization in the analog circuit design context.

Systematic Analysis and Research on Integrated Circuit Design Optimization

After decades of development of integrated circuits, there has been great progress in all aspects. These advances are reflected in the optimization of manufacturing processes and circuits. When designing a circuit, considering the production cost and the performance of the circuit, the optimal design of the circuit is always a very important link. In this paper, two kinds of optimization ideas are introduced. One is from the point of view of the physical design of the circuit, two methods are introduced, which are adjusting the input power and reducing the circuit device. The other is to optimize the circuit from the point of view of algorithm. Genetic algorithm and simulated annealing algorithm are introduced. After optimizing the circuit, the circuit energy consumption is reduced, the circuit delay is reduced, the circuit runs faster, and the overall performance is also improved. In the future, with the development of related technologies, the optimization of integrated circuits will be faster.

Topology optimization of analog circuit design via global optimization using factorization machines with digital annealer

Topology optimization of analog circuit design via global optimization using factorization machines with digital annealer

An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network

Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-μm Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 µW per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.

Circuit design and energy optimization strategy for a four-bit absolute value detector

The demands placed on the quality of products and services within the realm of electronic technology have reached unprecedented heights. The utilization of electronic decoders has thus become incredibly extensive to meet these evolving needs. Among the integral components of electronic decoders, the absolute value detector holds a significant position. In our pursuit to enhance the efficiency of electronic decoders, this paper have identified substantial room for improvement within the currently prevalent absolute value detector designs. This paper introduces a novel absolute value detector design scheme that promises remarkable advancements. It is worth noting that the performance of this newly proposed absolute value detector far surpasses that of the traditional counterparts. Through rigorous calculations and testing, our absolute value detector exhibits an impressive performance profile, boasting a delay of 34.13FO4 (1V) and an energy consumption of 184.832Eu (1V). These results undoubtedly hold the potential to catalyze innovation in digital decoder technology, offering fresh insights into how we can elevate the overall quality of digital decoders. This contribution paves the way for product enhancements and serves as a valuable resource for those striving to stay at the forefront of electronic technology advancements in our fast-paced information-driven society.

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

Application case and circuit design optimization of temperature and humidity control system by using Internet of Things

Application case and circuit design optimization of temperature and humidity control system by using Internet of Things

A Comprehensive Review of Bio-Inspired Optimization Algorithms Including Applications in Microelectronics and Nanophotonics.

The application of artificial intelligence in everyday life is becoming all-pervasive and unavoidable. Within that vast field, a special place belongs to biomimetic/bio-inspired algorithms for multiparameter optimization, which find their use in a large number of areas. Novel methods and advances are being published at an accelerated pace. Because of that, in spite of the fact that there are a lot of surveys and reviews in the field, they quickly become dated. Thus, it is of importance to keep pace with the current developments. In this review, we first consider a possible classification of bio-inspired multiparameter optimization methods because papers dedicated to that area are relatively scarce and often contradictory. We proceed by describing in some detail some more prominent approaches, as well as those most recently published. Finally, we consider the use of biomimetic algorithms in two related wide fields, namely microelectronics (including circuit design optimization) and nanophotonics (including inverse design of structures such as photonic crystals, nanoplasmonic configurations and metamaterials). We attempted to keep this broad survey self-contained so it can be of use not only to scholars in the related fields, but also to all those interested in the latest developments in this attractive area.