Optimize Power Dissipation Research Articles

Ciliary propulsion through non-uniform flows

The classical paper by Lighthill (Commun. Pure Appl. Maths, vol. 109, 1952, p. 118) on the propulsion of ciliated microorganisms has become the reference against which many modern studies on swimming in low Reynolds number are compared. However, Lighthill's study was limited to propulsion in a uniform flow, whereas several biologically relevant microorganisms experience non-uniform flows. Here we propose a benchmark for ciliary propulsion in paraboloidal flows. We first consider the axisymmetric problem, with the microorganisms on the centreline of the background flow, and derive exact analytical solutions for the flow field. Our results reveal flow features, swimming characteristics and performance metrics markedly different from those generated in a uniform flow. In particular, the background paraboloidal flow introduces a Stokes quadrupole singularity at the leading-order flow field, generating vortices. Moreover, we determine the necessary conditions on the strength of the background flow for optimal power dissipation and swimming efficiency. We then consider the more general case of a microorganism off the centreline of the background flow. In this case, the squirmer experiences a paraboloidal, linear shear and uniform flows due to its position relative to the flow's centreline. Our findings show that while the linear shear flow does not affect the translational and rotational velocities of the squirmer, it does influence the velocity field and, therefore, the power dissipation.

Regulation mechanism of bionic wireless power device thermal management system based on nanofluids and magnetic field

For further optimal power conservation and dissipation performance of wireless power devices, this paper presented a cooling system that couples a wave bionic surface structure with composite magnetic nanofluids. Heat transfer mechanisms near the wall of the channel under magnetic field excitation have been developed. Effect of changes in the near-wall thermal boundary layer on the integral heat transfer was analyzed, and a comprehensive evaluation of the model performance was given. The outcomes revealed that as the flow approaches the crest, the difference in thermal boundary layer thickness for different flow Reynolds numbers becomes small, and in the flow region in the second half of the wave crest, the thermal boundary depth is no longer regular at different Reynolds numbers, which is due to the “detached flow”. “Detached flow” effectively breaks the thermal boundary enhancing the heat transfer performance. Temperatures excited by magnetic forces show disordered “jumps”, and the heat transfer characteristics are substantially improved by 41.59 % under magnetic field. Comprehensive evaluation index under magnetic field excitation is up to 1.54 for wave bionic surfaces with a frequency of 20 rad/s.

Low power implementation of high frequency SiPM readout for Cherenkov and scintillation detectors in TOF-PET

State-of-the-art (SoA) electronic readout for silicon photomultiplier (SiPM)-based scintillation detectors that demonstrate experimental limits in achievable coincidence time resolution (CTR) leverage low noise, high frequency signal processing to facilitate a single photon time response that is near the limit of the SiPMs architecture. This readout strategy can optimally exploit fast luminescence and prompt photon populations, and promising measurements show detector concepts employing this readout can greatly advance PET detector CTR, relative to SoA in clinical systems. However, the technique employs power hungry components which make the electronics chain impractical for channel-dense time-of-flight (TOF)-PET detectors. We have developed and tested a low noise and high frequency readout circuit which is performant at low power and consists of discrete elements with small footprints, making it feasible for integration into TOF-PET detector prototypes. A 3 × 3 mm2 Broadcom SiPM with this readout chain exhibited sub-100 ps single photon time resolution at 10 mW of power consumption, with a relatively minor performance degradation to 120 ± 2 ps FWHM at 5 mW. CTR measurements with 3 × 3 × 20 mm3 LYSO and fast LGSO scintillators demonstrated 127 ± 3 ps and 113 ± 2 ps FWHM at optimal power operation and 133 ± 2 ps and 121 ± 3 ps CTR at 5 mW. BGO crystals 3 × 3 × 20 mm3 in size show 271 ± 5 ps FWHM CTR (1174 ± 14 ps full-width-at-tenth-maximum (FWTM)) at optimal power dissipation and 289 ± 8 ps (1296 ± 33 ps FWTM) at 5 mW. The compact and low power readout topology that achieves this performance thereby offers a platform to greatly advance PET system CTR and also opportunities to provide high performance TOF-PET at reduced material cost.

Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning

Design-space exploration for low-power manycore design is a daunting and time-consuming task which requires some complex tools and frameworks to achieve. In the presence of process variation, the problem becomes even more challenging, especially the time associated with trial-and-error selection of the proper options in the tools to obtain the optimal power dissipation. The key contribution of this work is the novel use of machine learning to speed up the design process by embedding the tool expertise needed for low power design-space exploration for manycores into a trained neural network. To enable this, we first generate a large volume of data for 36000 benchmark applications by running them under all possible configurations to find the optimal one in terms of power. This is done using our own tool called LVSiM, a holistic manycore optimization program including process variations. A neural network is trained with this information to build in the expertise. A second contribution of this work is to define a new set of features, relevant to power and performance optimization, when training the neural network. At design time, the trained neural network is used to select the proper options on behalf of the user based on the features of any new application. However, one problem encountered with this approach is that the database constructed for machine learning has many outliers due to randomness associated with process variation which creates a major headache for classification - the supervised learning task performed by neural networks. The third key contribution of this work is a novel data coercion algorithm used as a corrective measure to handle the outliers. The proposed data coercion scheme produces results that are within 3.9% of the optimal power consumption compared to 7% without data coercion. Furthermore, the proposed method is about an order of magnitude faster than a heuristic approach and two orders of magnitude faster than a brute-force approach for design-space exploration.

An optimization method for magnetic hyperthermia considering Nelder-Mead algorithm

Magnetic hyperthermia destroys malignant cells by absorbing the heat generated by magnetic nanoparticles (MNPs) under an external AC magnetic field. One of the most influencing factors for such therapy is to control the heat generation within MNPs, which is highly relevant to applied AC magnetic field and used MNPs during treatment. This paper optimizes the intensity of magnetic field acting on MNPs by considering an optimum power dissipation of MNPs, which is obtained by using Nelder-Mead algorithm for a proposed objective function during the optimization procedure. The aim of the proposed objective function is to minimize the difference between the maximum treatment temperature and its upper safety value as much as possible. The optimization results can be used to investigate the injury degree for the proposed model by Arrhenius thermal damage model, and also to optimize the performance for the magnetic field strength on MNPs by the implicit function due to Rosensweig’s theory in this study. Simulation results demonstrate that the power dissipation of MNPs can quickly converge to an optimum value after less iterations during the optimization process, which can also result in an ideal treatment temperature profile and can further obtain the injury degree for different malignant cells, when a temperature-dependent blood perfusion rate is considered for the simulation. The magnetic field or the MNPs can also be optimized before the therapy under this optimal power dissipation for MNPs at this time. In addition, this study also reveals the evolution of treatment temperature due to two blood perfusion rates, namely temperature-dependent and constant models.

Compact Thermal Modelling Tool for Fast Design Space Exploration of 3D ICs with Integrated Microchannels

Integrated microchannel cooling is a very promising concept for thermal management of 3D ICs, because it offers much higher cooling performance than conventional forced-air convection. The thermo-fluidic simulations of such chips are usually performed using a computational fluid dynamics (CFD) approach. However, due to the complexity of the fluid flow modelling, such simulations are typically very long and faster models are therefore considered. This paper demonstrates the advantages of TIMiTIC—a compact thermal simulator for chips with liquid cooling—and shows its practical usefulness in design space exploration of 3D ICs with integrated microchannels. Moreover, thermal simulations of a 3D processor model using the proposed tool are used to estimate the optimal power dissipation profile in the chip and to prove that such an optimal profile allows for a very significant (more than 10 °C) peak temperature reduction. Finally, a custom correlation metric is introduced which allows the comparison of the power distribution profiles in terms of the peak chip temperature that they produce. Statistical analysis of the simulation results demonstrates that this metric is very accurate and can be used for example in thermal-aware task scheduling or dynamic voltage and frequency scaling (DVFS) algorithms.

Emergent dynamics of neuromorphic nanowire networks

Neuromorphic networks are formed by random self-assembly of silver nanowires. Silver nanowires are coated with a polymer layer after synthesis in which junctions between two nanowires act as resistive switches, often compared with neurosynapses. We analyze the role of single junction switching in the dynamical properties of the neuromorphic network. Network transitions to a high-conductance state under the application of a voltage bias higher than a threshold value. The stability and permanence of this state is studied by shifting the voltage bias in order to activate or deactivate the network. A model of the electrical network with atomic switches reproduces the relation between individual nanowire junctions switching events with current pathway formation or destruction. This relation is further manifested in changes in 1/f power-law scaling of the spectral distribution of current. The current fluctuations involved in this scaling shift are considered to arise from an essential equilibrium between formation, stochastic-mediated breakdown of individual nanowire-nanowire junctions and the onset of different current pathways that optimize power dissipation. This emergent dynamics shown by polymer-coated Ag nanowire networks places this system in the class of optimal transport networks, from which new fundamental parallels with neural dynamics and natural computing problem-solving can be drawn.

Microprocessors optimal power dissipation using combined threshold hopping and voltage scaling

Microprocessors optimal power dissipation using combined threshold hopping and voltage scaling

Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator

Background: With the advent in hand held mobile computing devices, the demand for high performance compact processors is increasing. In this work a processor is designed with hardwired instructions for elementary mathematical functions like sine, cosine, sinh, cosh, division and multiplication. Methods: The processor employs Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of the above mentioned instructions. The parallel and pipelined implementation of the processor is carried out. The pipelined processor is configured as waveform generator. The novelty of this work is the integration of both trigonometric and hyperbolic operations in the same processor. Findings: ASIC Implementation is carried out with 40nm technology libraries. The parallel processor so designed operates at maximum frequency of 24.23 MHz and pipelined processor operates at maximum frequency of 261.36 MHz. Conclusion: This increase in operating frequency is achieved at the cost of increased silicon area and optimal power dissipation. The waveform generator generates sine, cosine waves of 3.5 MHz and sine hyperbolic, cosine hyperbolic waves and exponential waves of 7.9 MHz. The limitation being the waveform generator generates waves of constant frequency. Additional circuit is required in generating waves of different frequencies.

Hot forging characteristic of Ti–5Al–5V–5Mo–3Cr alloy with single metastable β microstructure

Hot deformation characteristic of Ti–5Al–5V–5Mo–3Cr alloy with a starting microstructure of an equiaxed single β microstructure is examined in relation to microstructural evolution and the result according to processing map technique. In testing at 700°C, subgrain formation is dominant at higher strain rate, while superplasticity occurs at lower strain rate. Herein, dynamic α precipitation from supersaturated β phase occurs during deformation and affects the flow behavior. In testing at and above 800°C, dynamic recovery (DRV) is dominant and continuous dynamic recrystallization (CDRX) also occurs especially in the vicinity of boundaries of prior-β-grains. There are three domains having an optimized power dissipation efficiency (ranging from 40% to 50%) in processing map. These three domains are reasonably explained in relation to microstructural conversion of frequent activations of grain boundary sliding, dynamic recovery and simultaneous occurrence of dynamic recovery and continuous dynamic recrystallization.

A PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTING

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.

Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool

Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from it’s switching activity, which is mainly influenced by the supply voltage and effective capacitance.[1,2,3] To optimize power dissipation, the researches show various techniques like appropriate coding, appropriate design architectures, appropriate manipulation algorithms. In this paper we have applied adiabatic logic design approach to design COMS inverter. Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at a circuit and logic level achieve reduction in power [12] Various adiabatic logic based inverters are shown. Mainly our aim is to design and simulate PFAL inverters. Finally we have calculated dissipated power of static CMOS inverter and compare it with that of PFAL based inverter. [4, 6]

Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.

A speaker driver for a single phase supply class G & I

A speaker driver applied to class G/class I with a single phase power supply is presented. Gain expanding and compressing technology are employed in the signal processing circuit to optimize power dissipation. The circuit is implemented in 0.18 μm N-well CMOS. Experimental results show that the speaker driver has a good audio sound quality and power efficiency. Less than 0.006% THD at a low power range and less than 0.4% at a medium power range can be obtained with a 1 kHz sine wave signal. Maximum output power of 360 mW can be gained at a load of 8 Ω. The power efficiency is about twice that of a traditional class AB driver at the power range of 80 mW and shows more than 18% improvement at the higher output power range.

Power Efficiency Improvement for Low Ohm Current Sense Resistor by Optimum Thermal Management

To improve power efficiency, design engineers need to detect current throughout the circuit to minimize power loss. Low ohm current sense resistors are used to detect current to measure and monitor power. These components need to handle higher power to achieve optimal performance. In this work, we extensively studied to improve the power handling capability of low ohm current sense resistors, while maintaining smaller size. We optimized power dissipation by applying innovative thermal management techniques. Employing novel packaging technique, we optimized heat dispersion and minimized the peak surface temperature rise. Using proprietary thermal protection material, we avoided direct heat transfer from component to PC board and minimize the risk of thermal damage against PCB and extreme thermal cycle. We extensively discussed the thermal fatigue of resistor termination structure. Solid metal package construction leads to solder cracks due to thermal fatigue, hence decreases resistor reliability. We improved the packaging footprint and significantly reduced the chance of solder cracking. We optimized the resistor structure for current sensing and shunting purpose. We laid out electrodes and termination in parallel and minimized the contact resistance. Considering these parameters, we manufactured low ohm current sense resistor of 0.5 milli ohm to 100 milli ohm values with up to 5W rated power with tolerance as low as 0.5%.

A 0.13 μm CMOS adaptive sigma–delta modulator for triple-mode GSM/Bluetooth/UMTS applications

This paper describes the design and experimental characterization of a 0.13μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80MHz), the internal quantization (1 or 2bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7dB at 400ksps/2/8Msps, respectively. The modulator power consumption is 23.9/24.5/44.5mW, of which 9.7/10/24.8mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.11This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2007-67247-C02-01/MIC and the Andalusian (Regional) Council of Innovation, Science and Enterprise under contract TIC-2532.

Optimal wire sizing of buffered global interconnects

PurposeThis paper aims to obtain the optimal wire sizing of buffered global interconnects and to investigate the impact of weight factor on the optimized system performance for various technology nodes.Design/methodology/approachThe width and spacing of interconnects are optimized under two scenarios, and corresponding optimum line width is determined by minimizing the value of power‐delay product which is defined as a figure of merit (FOM). Based on the results, the impact of weight factor on the optimized system performance, such as delay and power dissipation per unit length, is analyzed for various technology nodes.FindingsThe analytical expressions of the optimum width are derived under two scenarios. Better FOMs can be achieved for the S=W scenario, but the wireability of the chip degrades considerably. The optimized delay increases with the increasing of weight factor, while the optimized power dissipation decreases with it. For a given weight factor, smaller latency and less power dissipation can be achieved for the S=W case.Originality/valueThe analytical expressions of the optimum width of interconnects are given, and a comprehensive study of the impact of weight factor on the optimized results under two scenarios is presented.

Intensification of hydroxyl radical production in sonochemical reactors

The efficacy of sonochemical reactors in chemical processing applications has been well established in the laboratory scale of operation though at a given set of operating parameters and no efforts have been directed in terms of maximizing the free radical production. In the present work, the effect of different operating parameters viz. pH, power dissipation into the system, effect of additives such as air, haloalkanes, titanium dioxide, iron and oxygen on the extent of hydroxyl radical formation in a sonochemical reactor have been investigated using salicylic acid dosimetry. Possible mechanisms for oxidation of salicylic acid in the presence of different additives have also been established. It has been observed that acidic conditions under optimized power dissipation in the presence of iron powder and oxygen result in maximum liberation of hydroxyl radicals as quantified by the kinetic rate constant for production of 2,5- and 2,3-dihydroxybenzoic acid. The study has enabled the optimization of the conditions for maximum efficacy of sonochemical reactors where free radical attack is the controlling mechanism for the chemical processing applications.

Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets

This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipation with optimal delay constraints or with a given delay penalty. We derive optimal solutions for both cases. These solutions can be used to efficiently estimate the power dissipation for long single wires in the interconnect designs.

A CMOS line driver for ADSL central office applications

An ADSL central office (CO) line driver utilizing a single 6-V supply is described. The line driver output produces a 20-V/sub ppd/ signal to deliver a 40-V/sub ppd/ swing to a 100-/spl Omega/ line. The adoption of an active termination, a dynamic supply control circuit technique, and deep n-well devices at the output stage of the line driver is key in achieving such a large voltage swing in a 0.25-μm CMOS process. In order to ensure reliability of the output devices, the dynamic supply control algorithm is designed to activate only one lift amplifier at each signal path of the differential line driver at any given time. A transformer turns ratio of 1:2.4 ensures both reliability and optimal power dissipation in the presence of system losses. The total power dissipation of the line driver is 700 mW when discrete multitone signals with a crest factor of 15 dB were used to deliver 20.4 dBm to a 100-/spl Omega/ line.