Optimal wire sizing of buffered global interconnects

Abstract

PurposeThis paper aims to obtain the optimal wire sizing of buffered global interconnects and to investigate the impact of weight factor on the optimized system performance for various technology nodes.Design/methodology/approachThe width and spacing of interconnects are optimized under two scenarios, and corresponding optimum line width is determined by minimizing the value of power‐delay product which is defined as a figure of merit (FOM). Based on the results, the impact of weight factor on the optimized system performance, such as delay and power dissipation per unit length, is analyzed for various technology nodes.FindingsThe analytical expressions of the optimum width are derived under two scenarios. Better FOMs can be achieved for the S=W scenario, but the wireability of the chip degrades considerably. The optimized delay increases with the increasing of weight factor, while the optimized power dissipation decreases with it. For a given weight factor, smaller latency and less power dissipation can be achieved for the S=W case.Originality/valueThe analytical expressions of the optimum width of interconnects are given, and a comprehensive study of the impact of weight factor on the optimized results under two scenarios is presented.