Optimal Wire Width Research Articles

Theoretical analysis and modeling of photoemission ability and photoelectric conversion characteristics of GaAs nanowire cathodes based on photon-enhanced thermionic emission

An axially exponential-doping GaAs nanowire cathode is proposed as the cathode material of photon-enhanced thermionic emission (PETE) device. Two-type theoretical models are respectively developed based on the numerical solution of multi-dimensional continuous equations with the boundary conditions. The quantum efficiency and the conversion efficiency of exponential-doping GaAs nanowire cathode based on PETE mechanism as a function of wire length, wire width, operating temperature, emissive surface recombination velocity and surface electron affinity are simulated and analyzed, respectively. Results show that the PETE devices with exponential-doping cathode can exhibit more superiority than those with uniform-doping structure by comparing the conversion efficiency, which mainly attributes to the built-in electric field induced by the axially exponential-doping structure. In addition, the optimal wire height and wire width for exponential-doping GaAs nanowire cathode are about 6 μm and 300 nm, respectively. Moreover, the emissive surface recombination velocity has an obvious inhibition on the quantum efficiency and conversion efficiency of GaAs nanowire PETE devices. The simulations would provide valuable theoretical guidance to achieve high-performance nano-based PETE devices.

The Role of Rayleigh-Wood Anomalies and Surface Plasmons in Optical Enhancement for Nano-Gratings

We propose and report on the design of a 1-D metallo-dielectric nano-grating on a GaAs substrate. We numerically study the impact of grating period, slit and wire widths, and irradiating angle of incidence on the optical response. The optimal wire width, w = 160 nm, was chosen based on previous results from investigations into the influence of wire width and nano-slit dimensions on optical and electrical enhancements in metal-semiconductor-metal photodetectors. In this present project, resonant absorption and reflection modes were observed while varying the wire and nano-slit widths to study the unique optical modes generated by Rayleigh-Wood anomalies and surface plasmon polaritons. We observed sharp and diffuse changes in optical response to these anomalies, which may potentially be useful in applications such as photo-sensing and photodetectors. Additionally, we found that varying the slit width produced sharper, more intense anomalies in the optical spectrum than varying the wire width.

Multi-Layer Interdigitated Power Distribution Networks

Higher operating frequencies and greater power demands have increased the requirements on the power and ground network. Simultaneously, due to the larger current loads, current densities are increasing, making electromigration an important design issue. In this paper, methods for optimizing a multi-layer interdigitated power and ground network are presented. Based on the resistive and inductive (both self- and mutual) impedance, a closed-form solution for determining the optimal power and ground wire width is described, producing the minimum impedance for a single metal layer. Electromigration is considered, permitting the appropriate number of metal layers to be determined. The tradeoff between the network impedance and current density is investigated. Based on 65-, 45-, and 32-nm CMOS technologies, the optimal width as a function of metal layer is determined for different frequencies, suggesting important trends for interdigitated power and ground networks.

Optimal Global Interconnects for Networks-on-Chip in Many-Core Architectures

While integrated circuits are moving toward many-core architectures, no circuit-aware interconnect technology optimization methodology has been reported for such chips. To utilize a many-core chip to its full potential, low-latency ultrahigh-bandwidth intercore interconnects are needed. In this letter, for the first time, interconnect dimensions in a network-on-chip (NoC) are optimized to achieve large bandwidth density and small latency simultaneously. The optimal wire width for a NoC is found to be more than ten times smaller than the previously obtained optimal global interconnect width. For a 1000-core chip implemented in the technology year 2015, the optimal wire width is found to be minimum-dimension limited.

Subband anticrossing and the spin Hall effect in quantum wires

We report on numerical simulations of the intrinsic spin Hall effect in semiconductorquantum wires as a function of the Rashba spin–orbit coupling strength, the electrondensity, and the width of the wire. We find that the strength of the spin Hall effectdoes not depend monotonically on these parameters, but instead exhibits a localmaximum. This behavior is explained by considering the dispersion relation ofthe electrons in the wire, which is characterized by the anticrossing of adjacentsubbands. These results lead to a simple estimate of the optimal wire width for spinHall transport experiments, and simulations indicate that this optimal width isindependent of disorder. The anticrossing of adjacent subbands is related to a quantumphase transition in momentum space, and is accompanied by an enhancement ofthe Berry curvature and subsequently in the magnitude of the spin Hall effect.

Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning

As VLSI circuits are scaled into advanced deep-submicron (DSM) dimensions, interconnection delay plays an important role for any performance-driven design. In general, the techniques of wire sizing and buffer insertion can be further used to reduce the timing delay of any interconnection net. Basically, the concept of uniform wire sizing cannot lead to the timing optimisation of any interconnection net. On the basis of the analysis of optimal wire width on one wire segment, the wire planning with optimal wire widths is proposed to use less routing area to reduce the timing delay of any interconnection net. Furthermore, given a compact floorplan with a set of interconnection nets, on the basis of the analysis of buffer locations on one wire segment and the construction of a recursive buffer-location graph, an area-driven buffer block planning with optimal wire sizing (ABBP_OWS) algorithm is proposed to insert the feasible buffers into the given floorplan for each net without destroying the timing constraint of any routing net, and the time complexity of the proposed ABBP_OWS algorithm is proved to be O(mn2), where m is the number of interconnection nets and n is the number of circuit blocks in the floorplan. Finally, the experimental results show that the proposed ABBP_OWS algorithm uses less routing area and floorplan area to meet more interconnection nets on all the tested benchmark circuits for interconnect-driven floorplanning.

Compact Physical Models for Multilevel Interconnect Crosstalk in Gigascale Integration (GSI)

For the first time, compact physical models are derived for crosstalk noise of coplanar resistance-inductance-capacitance lines in a gigascale integration (GSI) chip that simultaneously consider far and near aggressors in both the same metal level and distant metal levels. Since both the amplitude and duration of noise are important, the noise voltage-time integral can be defined as a figure-of-merit for crosstalk, and it is shown that this integral attains its maximum at the length at which the interconnect resistance becomes equal to twice the characteristic impedance. It is also shown that crosstalk can be prohibitively large if interconnects have small resistances. There is, therefore, a tradeoff between interconnect latency and crosstalk. The compact models are finally used to calculate the crosstalk noise voltage for the case that wire width is optimized by simultaneously maximizing data flux density and minimizing latency. It has been proven that by utilizing the optimal wire width for signal interconnects and twice of that for power and ground lines, the worst case peak crosstalk noise voltage becomes smaller than 0.25 V/sub dd/ for all generations of technology.

Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).

Maximizing throughput over parallel wire structures in the deep submicrometer regime

In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in submicron technologies.

Wire width planning for interconnect performance optimization

In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of globally optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a globally optimal wire width design and show rather surprisingly that using only two predesigned widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures.

EWA: efficient wiring-sizing algorithm for signal nets and clock nets

The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable transformation. Due to their efficiency and ease of implementation, one-wire-at-a-time downhill improvement heuristics are often applied to solve such problems. Unfortunately, when there are complex boundary constraints, the solutions from such heuristics can be far away from the global minimum. There are formal methods for solving convex programs, but they are too costly in terms of runtime for some applications. Some optimization techniques can be quite efficient but they solve less desirable formulations, such as minimum weighted sum of area and critical path delays. This paper proposes an efficient wire-sizing algorithm (EWA) that is able to trade solution accuracy for time efficiency while providing an upper bound on the distance from the optimal solution. EWA solves the practical problem of minimizing the total wiring area or the capacitance of an interconnect RC tree subject to hard constraints on the Elmore delay. The implementation is simple and efficiency is comparable to the available heuristics. No restrictions are placed on the circuit or wire widths. Furthermore, it is shown that the optimal wire width assignment for a minimum wiring area objective satisfies all the delay constraints as equalities when minimum wire width constraints are not active. It follows that EWA can be applied for problems with equality delay constraints such as clock trees. Moreover, this and other properties are general enough to permit extensions to higher order delay models and can be used to enhance other optimization methods.