Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning

Abstract

As VLSI circuits are scaled into advanced deep-submicron (DSM) dimensions, interconnection delay plays an important role for any performance-driven design. In general, the techniques of wire sizing and buffer insertion can be further used to reduce the timing delay of any interconnection net. Basically, the concept of uniform wire sizing cannot lead to the timing optimisation of any interconnection net. On the basis of the analysis of optimal wire width on one wire segment, the wire planning with optimal wire widths is proposed to use less routing area to reduce the timing delay of any interconnection net. Furthermore, given a compact floorplan with a set of interconnection nets, on the basis of the analysis of buffer locations on one wire segment and the construction of a recursive buffer-location graph, an area-driven buffer block planning with optimal wire sizing (ABBP_OWS) algorithm is proposed to insert the feasible buffers into the given floorplan for each net without destroying the timing constraint of any routing net, and the time complexity of the proposed ABBP_OWS algorithm is proved to be O(mn2), where m is the number of interconnection nets and n is the number of circuit blocks in the floorplan. Finally, the experimental results show that the proposed ABBP_OWS algorithm uses less routing area and floorplan area to meet more interconnection nets on all the tested benchmark circuits for interconnect-driven floorplanning.