Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance

Abstract

In this paper, given a set of connecting nodes in a signal net, based on the result of optimal wire width and buffer insertion in a wire segment (Yan, 2006) and the concept of sharing-buffer insertion and hidden Steiner-point assignment, an effective tree construction approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing, buffer insertion and obstacle avoidance. The experimental results show that our proposed approach obtains better timing-driven Steiner trees than our previous approach (Dechu et al., 2004) for the tested signal nets.