Optical Proximity Correction Research Articles

How to make lithography patterns print: the role of OPC and pattern layout

Abstract This paper will review some of the methods that have been devised to bring lithography-generated patterns as close to the desired target patterns as possible, while making them also robust against inevitable deviations from the ideal conditions during the printing process. Optical proximity correction (OPC) is the first step in this process. Various ways have been developed for efficient creation of accurate process window aware OPC models. Also, the use of the actual OPC step, to transform the target patterns into actual lithography mask patterns has seen significant progress. A computational verification step then checks whether the predicted pattern shapes meet the quality requirements and identifies any residual failures or weak patterns (‘hotspots’). Once the mask is available, a second verification step, now looking at patterns on printed wafers, is performed to make sure that all critical patterns print to within the requested tolerances. Each of the steps in this flow can – and usually does – lead to corrective iterations to one of the previous steps. As the task of ensuring sufficient process margin is gradually becoming more difficult, with the ever decreasing pattern sizes, constraints are being increasingly defined on the type of patterns that can be allowed in the target layout itself (design restrictions), leading to a tendency toward more regular designs, an evolution that needs to be facilitated by the patterning technology and materials used. So the problem of ensuring good printability now also involves both layout and technology, and we will look into this aspect of the optimization problem as well.

Fast and accurate lithography simulation using cluster analysis in resist model building

As technology nodes continue to shrink, optical proximity correction (OPC) has become an integral part of mask design to improve the subwavelength printability. The success of lithography simulation to perform OPC on an entire chip relies heavily on the performance of lithography process models. Any small enhancement in the performance of process models can result in a valuable improvement in the yield. We propose a robust approach for lithography process model building. The proposed scheme uses the clustering algorithm for model building and thereby improves the accuracy and computational efficiency of lithography simulation. The effectiveness of the proposed method is verified by simulating some critical layers in 14- and 22-nm complementary metal oxide semiconductor technology nodes. Experimental results show that compared with a conventional approach, the proposed method reduces the simulation time by 50× with ∼5% improvement in accuracy.

Enabling scanning electron microscope contour-based optical proximity correction models

A scanning electron microscope (SEM) is the metrology tool used to accurately characterize very fine structures on wafers, usually by extracting one critical dimension (CD) per SEM image. This approach for optical proximity correction (OPC) modeling requires many measurements resulting in a lengthy cycle time for data collection, review, and cleaning, and faces reliability issues when dealing with critical two-dimensional (2-D) structures. An alternative to CD-based metrology is to use SEM image contours for OPC modeling. To calibrate OPC models with contours, reliable contours matched to traditional CD-SEM measurements are required along with a method to choose structure and site selections (number, type, and image space coverage) specific to a contour-based OPC model calibration. The potential of SEM contour model-based calibration is illustrated by comparing two contour-based models to reference models, one empirical model and a second rigorous simulation-based model. The contour-based models are as good as or better than a CD-based model with a significant advantage in the prediction of complex 2-D configurations with a reduced metrology work load.

Forming Freeform Source Shapes by Utilizing Particle Swarm Optimization to Enhance Resolution in Extreme UV Nanolithography

This paper investigated pixel-based source shape optimization to enhance the resolution in a projection extreme UV (EUV) lithography system. The particle swarm optimization method was proposed to optimize the source shapes. The layout patterns of the masks were corrected using model-based optical proximity correction. The optimal source shape in an EUV lithography system was verified using numerical calculations, through which the aerial image of two types of mask pattern exposure was determined. The two types of mask patterns were a logic line/space (L/S) pattern with a critical dimension (CD) of 16 nm and a SRAM contact hole (CH) pattern with a CD of 45 nm. Two significant metrics were used to evaluate the modified source performance: the latent image intensity and process window. Results from the numerical calculations showed that for L/S target patterns, using the optimal source produced a latent image error of 13.02% after exposure that was superior to that of traditional off-axis source exposure. The latent image intensity of the mask between the lines and the gaps differed substantially, corner rounding situations had effectively improved, and no bridges were observed. Concerning CH target patterns, using the optimal source produced a latent image error of 0.04% after exposure that was also superior to that of traditional sources. The latent image intensity between the holes and the gaps also differed significantly, and the latent image intensity distribution at the four corners of the CH had straight angles. Because the source shapes calculated in this study comprised pixel-based sources, the controllable microelectromechanical system mirror array chip was used to match each mirror to each pixel source, and the calculated source shapes were successfully projected.

Micro-optics and lithography simulation are key enabling technologies for shadow printing lithography in mask aligners

Abstract Mask aligners are lithographic tools used to transfer a pattern of microstructures by shadow printing lithography onto a planar wafer. Contact lithography allows us to print large mask fields with sub-micron resolution, but requires frequent mask cleaning. Thus, contact lithography is used for small series of wafer production. Proximity lithography, where the mask is located at a distance of typically 30–100 μm above the wafer, provides a resolution of approximately 3–5 μm, limited by diffraction effects. Proximity lithography in mask aligners is a very cost-efficient method widely used in semiconductor, packaging and MEMS manufacturing industry for high-volume production. Micro-optics plays a key role in improving the performance of shadow printing lithography in mask aligners. Refractive or diffractive micro-optics allows us to efficiently collect the light from the light source and to precisely shape the illumination light (customized illumination). Optical proximity correction and phase shift mask technology allow us to influence the diffraction effects in the aerial image and to enhance resolution and critical dimension. The paper describes the status and future trends of shadow printing lithography in mask aligners and the decisive role of micro-optics as key enabling technology.

Efficient three-dimensional resist profile-driven source mask optimization optical proximity correction based on Abbe-principal component analysis and Sylvester equation

As one of the critical stages of a very large scale integration fabrication process, postexposure bake (PEB) plays a crucial role in determining the final three-dimensional (3-D) profiles and lessening the standing wave effects. However, the full 3-D chemically amplified resist simulation is not widely adopted during the postlayout optimization due to the long run-time and huge memory usage. An efficient simulation method is proposed to simulate the PEB while considering standing wave effects and resolution enhancement techniques, such as source mask optimization and subresolution assist features based on the Sylvester equation and Abbe-principal component analysis method. Simulation results show that our algorithm is 20× faster than the conventional Gaussian convolution method.

Resist toploss and profile modeling for optical proximity correction applications

As critical dimensions decrease for 32-nm node and beyond, the resist loss increases and resist patterns become more vulnerable to etching failures. Traditional optical proximity correction (OPC) models only consider two-dimensional (XY) contours and neglect height (Z) variations. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip. However, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. We show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and, in some cases, for correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3-D effects like diffusion through height.

Fast pixel-based optical proximity correction based on nonparametric kernel regression

Optical proximity correction (OPC) is a resolution enhancement technique extensively used in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. In pixel-based OPC (PBOPC), the layout is divided into small pixels, which are then iteratively modified until the simulated print image on the wafer matches the desired pattern. However, the increasing complexity and size of modern integrated circuits make PBOPC techniques quite computationally intensive. This paper focuses on developing a practical and efficient PBOPC algorithm based on a nonparametric kernel regression, a well-known technique in machine learning. Specifically, we estimate the OPC patterns based on the geometric characteristics of the original layout corresponding to the same region and a series of training examples. Experimental results on metal layers show that our proposed approach significantly improves the speed of a current professional PBOPC software by a factor of 2 to 3, and may further reduce the mask complexity.

Optical proximity correction using holographic imaging technique

In this work, the preliminary results of the holographic imaging technique (HIT) as a resolution enhancement technique (RET) hybrid inverse lithography technique (ILT) optical proximity correction mask correction is presented. The proposed technique is based on the illumination system and free space propagation of the mask. First, an in-line hologram (Gabor hologram) is generated by computing the target pattern diffraction pattern. Second, the computed hologram is synthesized as pattern contours to form a mask for a conventional optical system. In this study, a simple HIT corrected mask is validated with compact lithographic exposure system mathematical model for demonstrating the preliminary validity of the proposed method. Future plans to validate HIT for the most aggressive process nodes are proposed. The proposed technique has not been exercised against conventional ILT or other RET techniques, and does not contain analysis of resolution improvement achievable with those techniques.

Computational simulations and parametric studies for directed self-assembly process development and solution of the inverse directed self-assembly problem

Approaches to the computational simulation of directed self-assembly (DSA) of block copolymers based on Monte-Carlo methods and self-consistent field theory are presented and reviewed, with an emphasis on computational models of DSA processes usable for fabrication of integrated circuits (ICs). Applications of such models are illustrated by presenting the results of simulations used in the development of DSA fabrication processes. The inverse DSA problem, or DSA proximity correction (DSA PC) problem, is formulated, and the methods for its computational solution are presented. The application of one of these methods is illustrated by demonstrating co-optimization of optical proximity correction (OPC) and DSA PC for IC vias fabricated using a graphoepitaxy DSA process.

SVM based layout retargeting for fast and regularized inverse lithography

Inverse lithography technology (ILT), also known as pixel-based optical proximity correction (PB-OPC), has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the traditional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine (SVM) based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the ‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manufacturability is another critical issue in ILT; however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT (LSB-ILT) algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8% and 69.0%, respectively.

Topology optimization for optical projection lithography with manufacturing uncertainties

This article presents a topology optimization approach for micro- and nano-devices fabricated by optical projection lithography. Incorporating the photolithography process and the manufacturing uncertainties into the topology optimization process results in a binary mask that can be sent directly to manufacturing without additional optical proximity correction (OPC). The performance of the optimized device is robust toward the considered process variations. With the proposed unified approach, the design for photolithography is achieved by considering the optimal device performance and manufacturability at the same time. Only one optimization problem is solved instead of two as in the conventional separate procedures by (1)blueprint design and (2)OPC. A micro-gripper design example is presented to demonstrate the potential of this approach.

Co-optimization of the mask, process, and lithography-tool parameters to extend the process window

Optimization technologies have been widely applied to improve lithography performance, such as optical proximity correction and source mask optimization (SMO). However, most published optimization technologies were performed under fixed process conditions, and only a few parameters were optimized. A method for mask, process, and lithography-tool parameter co-optimization (MPLCO) is developed to extend the process window. A normalized conjugate gradient algorithm is proposed to improve the convergence efficiency of the MPLCO when optimizing different scale parameters. In addition, a parametric mask and source are used in the MPLCO that could obtain exceedingly low mask and source complexity compared with a traditional SMO.

The Mask 3D Effect on 2D Pattern Shape Fidelity, a Simulation Study

Mask 3D effect has been viewed as a drawback to the pattern fidelity with major characteristics in higher mask error factor (MEF), lower image contrast, or exposure latitude (EL), and reduced common depth of focus (DOF) between dense and semi-dense patterns. Recently, we found that the mask 3D scattering can also result in pattern shape variation, which can make optical proximity correction (OPC) less difficult. We use both thin mask simulation and the 3D mask simulation tools on a regular proximity test pattern of contact holes and found that the holes are usually elliptical and the degree of ellipse is primarily dependent on the relative image contrast values in the mutually orthogonal dimensions, or X and Y directions. And we found through simulation that the mask 3D scattering can reduce the imaging contrast in the relatively speaking denser dimension, which will make the contact look more round.

An Investigation on OPC Model Coverage to Improve CD Uniformity

Model-based Optical Proximity Correction (model-based OPC) has become a necessity for state of the art IC fabrication at advanced node technology. It needs one “reliable” OPC model for successful application of model-based OPC. Namely, the reliable OPC model needs to have much wider coverage and high accuracy to characterize the physical processes that take place during the photoresist exposure and development. One of the key factors for reliability of OPC model is model coverage which depends strongly on test pattern samples for model calibration. In this paper, two sets of test structures were selected to do OPC model calibration to qualify CD uniformity of patterns in array structures at 3xnm technology node. The results show the intermediate number of features for a given pitch is necessary for wider coverage of OPC model. The model including such patterns can improve CD uniformity of array structure. One methodology to design optimal permutation and combination for test patterns is proposed.

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction

Silicon physically unclonable functions (PUFs) are circuits that exploit modern manufacturing variations to generate unique signatures for chip authentication and cryptographic key generation. Existing research has focused on improving PUF quality at architectural or design levels, but has ignored opportunities available during fabrication, which is the source of systematic and random variation in (ICs)/PUFs. For typical ICs (where security is not a concern), optical proximity correction (OPC) is used to suppress both these types of variations. However, several prior works have shown that only systematic variations negatively impact PUF quality and random variations are beneficial for PUFs. In this paper, we propose two PUF-aware OPC cost functions: 1) P-OPC generates a PUF lithography mask that increases all variations in PUF circuitry (the opposite of state-of-the-art OPC), and 2) SVC-OPC generates mask patterns that reduce the systematic variation found in PUFs for better quality. Simulation results for ring oscillator (RO) PUFs show that the proposed techniques can improve PUF signature quality compared to current state-of-the-art OPC.

A Technique for the Non-Destructive EUV Mask Sidewall Angle Measurement Using Scanning Electron Microscope

EUV mask absorber sidewall angle should be measured for mask Optical Proximity Correction and shadow effect estimation. Hence, verifying the three-dimensional profile of mask topography has become a challenge in EUV mask inspection. This paper evaluates EUV mask sidewall angle measurement by Field-Emission Critical Dimension (CD)-Scanning Electron Microscope (SEM) using JEOL JSM-7401F. SEM only produces two-dimensional gray images. Forming three-dimensional profiles from these images is a critical requirement for the sidewall angle measurement. To obtain three-dimensional information, absorber edge width has to be measured first to measure sidewall angle. We can calculate absorber sidewall angle with the exactly measured edge width and absorber height. Edge width narrows with steeper sidewall angle. We used the image processing function of Matlab to obtain absorber edge width accurately. In the end, every measured sidewall angle was compared to Transmission Electron Microscope (TEM) images to evaluate the validity of SEM results. Measured sidewall angles by SEM and TEM cross-section images have average tolerances of 0.62 degrees.

Regularized level-set-based inverse lithography algorithm for IC mask synthesis

Inverse lithography technology (ILT) is one of the promising resolution enhancement techniques, as the advanced IC technology nodes still use the 193 nm light source. In ILT, optical proximity correction (OPC) is treated as an inverse imaging problem to find the optimal solution using a set of mathematical approaches. Among all the algorithms for ILT, the level-set-based ILT (LSB-ILT) is a feasible choice with good production in practice. However, the manufacturability of the optimized mask is one of the critical issues in ILT; that is, the topology of its result is usually too complicated to manufacture. We put forward a new algorithm with high pattern fidelity called regularized LSB-ILT implemented in partially coherent illumination (PCI), which has the advantage of reducing mask complexity by suppressing the isolated irregular holes and protrusions in the edges generated in the optimization process. A new regularization term named the Laplacian term is also proposed in the regularized LSB-ILT optimization process to further reduce mask complexity in contrast with the total variation (TV) term. Experimental results show that the new algorithm with the Laplacian term can reduce the complexity of mask by over 40% compared with the ordinary LSB-ILT.

A novel OPC method to reduce mask volume with yield-aware dissection

Growing data volume of masks tremendously increases manufacture cost. The cost increase is partially due to the complicated optical proximity corrections applied on mask design. In this paper, a yield-aware dissection method is presented. Based on the recognition of yield related mask context, the dissection result provides sufficient degrees of freedom to keep fidelity on critical sites while still retaining the frugality of modified designs. Experiments show that the final mask volume using the new method is reduced to about 50% of the conventional method.

Deep sub-wavelength imaging lithography by a reflective plasmonic slab

By utilizing a reflective plasmonic slab, it is demonstrated numerically and experimentally in this paper deep sub-wavelength imaging lithography for nano characters with about 50 nm line width and dense lines with 32 nm half pitch resolution (about 1/12 wavelength). Compared with the control experiment without reflective plasmonic slab, resolution and fidelity of imaged resist patterns are remarkably improved especially for isolated nano features. Further numerical simulations show that near field optical proximity corrections help to improve imaging fidelity of two dimensional nano patterns.