Optical Network-on-chip Research Articles

Low Polling Time TDM ONoC With Direction-Based Wavelength Assignment

Optical network-on-chip (ONoC) is a promising technology for future on-chip many-core communications. ONoC can achieve high bandwidth density and low communication latency under low network cost, which leads to an energy-efficient network. Time-division multiplexing (TDM)-based ONoC aims to solve the congestion problem faced by many optical circuit switching (OCS)-based mesh ONoCs. But TDM-based ONoC still suffers fromhigh network polling time, which causes high average network latency, especially under low network load. In this paper, we propose a novel TDMONoC using torus topology and direction-based wavelength assignment, named TTWA. TTWA ONoC combines TDM communication strategy and torus network topology to solve the congestion problem under the heavy network load faced by OCS-based ONoCs.With the utilization of direction-based wavelength assignment and torus topology, we further propose a high-efficiency communication strategy to improve the adjacent inter-cluster parallel communications and decrease the total TDM slot number, which contributes to a smaller network polling time and lower average network latency. A novel optical router is simultaneously designed to meet the communication strategy in TTWA. The analyses and simulation results indicate that TTWA ONoCimproves the polling time compared with other TDM-based ONoCs and achieves better network performance compared with the equivalent OCS-based ONoCs under various synthetic traffic patterns and realistic scientific applications. After the calculation,TTWA ONoC reduces the network insertion loss of OCS-based mesh ONoC 46.92% and that of OCS-based torus ONoC 31.75% and reduces the required laser power of OCS-based mesh ONoC 62.90% and that of OCSbased torus ONoC 40.66% under the worst-case situation.

Optical Overlay NUCA

In this article, we propose using optical networks-on-chip (NoCs) to design cache access protocols for large shared L2 caches. We observe that the problem is unique because optical networks have very low latency, and in principle all of the cache banks are very close to each other. A naive approach is to broadcast a request to a set of banks that might possibly contain the copy of a block. However, this approach is wasteful in terms of energy and bandwidth. Hence, we propose a set of novel schemes that create a set of virtual networks ( overlays ) of cache banks over a physical optical NoC. We search for a block inside each overlay using a combination of multicast and unicast messages. We first propose two simple protocols: TSI and Broadcast . The former uses unicast messages, and the latter uses multicast messages. We subsequently propose an improved scheme, OP_BCAST , that combines the best of TSI and Broadcast , and mainly uses restricted multicast messages. Then we propose a set of novel hardware structures for creating and managing overlays, for efficiently locating blocks in the overlay, and for implementing dynamically changing overlays with OP_BCAST . The performance of the TSI scheme is within 2% to 3% of a broadcast scheme, and it is faster than traditional schemes with electrical networks by 26%. Compared to the broadcast scheme, it reduces the number of accesses, and consequently the dynamic energy of the caches by 6% to 8%. OP_BCAST is 34% faster than the best solutions with copper-based NoCs; moreover, it reduces the dynamic energy for cache access by 33% compared to the TSI scheme.

Designs of 3D mesh and torus optical Network-on-Chips: Topology, optical router and routing module

As a nanometer-level interconnection, the Optical Network-on-Chip (ONoC) was proposed since it was typically characterized by low latency, high bandwidth and power efficiency. Compared with a 2-Dimensional (2D) design, the 3D integration has the higher packing density and the shorter wire length. Therefore, the 3D ONoC will have the great potential in the future. In this paper, we first discuss the existing ONoC researches, and then design mesh and torus ONoCs from the perspectives of topology, router, and routing module, with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate, and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally, we summarize some future challenges with possible solutions, including microcosmic routing inside optical routers and highly-efficient traffic grooming.

Time-Division-Multiplexing–Wavelength-Division-Multiplexing-Based Architecture for ONoC

Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the continually increasing number of cores on one chip. Optical networkon- chip (ONoC) is employed as a promising candidate interconnection solution for its high bandwidth and low energy consumption. However, optical circuit-switching (OCS) based architectures face the problem of high network congestion, low network utilization, and an overhead in power dissipation under heavy loads. In this paper, we propose an ONoC architecture with time-division multiplexing (TDM) and wavelength-division multiplexing (WDM) technology to solve the network contention problem faced by OCSbased ONoC. The number of wavelength groups and timeslots is optimized by using a genetic algorithm. A new optical router is designed to realize our TDM–WDM communication technology. A detailed model is built to analyze insertion loss and crosstalk noise. The simulation results show that TDM–WDM-based ONoC has better performance compared with equivalent OCS-mesh ONoC under a uniform traffic pattern. Similar analysis can be drawn for the real science application based on the PARSEC benchmark.

Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip

With the ever-growing core counts in modern computing systems, networks-on-chip (NoCs) consume an increasing part of the power budget due to bandwidth and power density limitations of electrical interconnects. To maintain performance and power scaling, alternative technologies are required, with silicon photonics being a promising candidate thanks to high-bandwidth, lowenergy data transmission. To get the best of silicon photonics, sophisticated network designs are required to minimize static power overheads. In this paper, we propose Amon, a low-power optical NoC that decreases the number of μRings, wavelengths, and path losses to reduce power consumption. Amon performs destination checking prior to data transmission on an underlying control network, allowing the sharing of optical bandwidth. Compared to a wide range of state-of-the-art optical, hybrid, and electrical NoCs, Amon improves throughput-per-watt by at least 23% (up to 70%), while reducing power without latency overheads on both synthetic and realistic applications. For aggressive optical technology parameters, Amon considerably outperforms all alternative NoCs in terms of power, highlighting its increasing superiority as technology matures.

Nesting ring architecture of multichip optical network on chip for many-core processor systems

Optical network on chip (ONoC) is an attractive solution for multicore/many-core processor systems due to its high power efficiency and enormous bandwidth. However, as increasing numbers of cores need to be interconnected, the scalability of a many-core processor on a single chip is limited by its process yield and power density. A multichip architecture is, therefore, proposed to improve the scalability of ONoC. In multichip architectures, the throughput and traffic delay rely on both the intrachip and interchip networks. To exploit the advantages of multichip systems, first we propose a multichip ONoC architecture for a many-core processor system that employs a nesting ring topology. The design principles of multichip systems of different sizes are then investigated to achieve higher throughput and lower delay. These principles include the number of chips and the number of cores per chip, which are considered jointly for the first time. Finally, we evaluate the performance of the proposed architecture, implemented in 240-core and 400-core systems, respectively, and compare it to two other traditional ONoC architectures with respect to throughput and end-to-end (ETE) delay. The results show that the proposed multichip system exhibits good scalability, achieves high throughput, and provides low ETE delay.

Reliable communications in optical network-on-chip by use of fault tolerance approaches

We present schemes for reliable communications in Optical Networks on Chip (ONoC) through employing information redundancy and hardware redundancy. By means of optical parity generators, SNR associated errors can be detected at the destinations. Besides SNR-based faults, thermal sensitivity of micro ring resonators can be a threat to the communications reliability. Thermal stabilization methods because of consuming large portion of the on-chip power, directly affect the power efficiency of the optical NoC. Hence, in this paper, using redundant rings which perform in different thermal variations is proposed to reduce the thermal variations-based errors. Simulation results demonstrate that using parity generators in the photonic layer although imposing higher energy consumption to this plane, it reduces the latency overhead about 16% in compared with their electrical counterpart. Moreover, redundancy technique can achieve 20% improvement in power consumption with negligible area overhead.

Coupling erbium dopants in yttrium orthosilicate to silicon photonic resonators and waveguides.

A scalable platform for on-chip optical quantum networks will rely on standard top-down nanofabrication techniques and solid-state emitters with long coherence times. We present a new hybrid platform that integrates amorphous silicon photonic waveguides and microresonators fabricated on top of a yttrium orthosilicate substrate doped with erbium ions. The quality factor of one such resonator was measured to exceed 100,000 and the ensemble cooperativity was measured to be 0.54. The resonator-coupled ions exhibited spontaneous emission rate enhancement and increased coupling to the input field, as required for further development of on-chip quantum light-matter interfaces.

MRONoC: A Low Latency and Energy Efficient on Chip Optical Interconnect Architecture

The circuit switched optical network on chip (ONoC) is popularly employed since the optical buffer is not available. However, this technique suffers from limited transmission bandwidth, high setup-time overhead, and high network resource contention, which consequentially induces long latency and degraded throughput. In this paper, we propose a new ONoC architecture aiming at ultralow setup cost, improved scalability, and contention-free communication. We first utilize wavelength division multiplexing (WDM) to introduce the basic version of this ONoC with efficient wavelength assignment. A series of potential versions are developed by using multiple waveguides to relieve the pressure on the number of wavelengths. These potential versions can make a tradeoff between required wavelengths and waveguides and improve the scalability. The new architectures employ two layers relying on the interlayer coupler, which contributes to the decrease of crossing losses. The simulation results show that the architecture can achieve 133% saturated bandwidth improvement compared with the traditional mesh ONoC employing WDM technology under the uniform traffic pattern.

H2ONoC: A Hybrid Optical–Electronic NoC Based on Hybrid Topology

Next-generation chip multiprocessors will require communication performance levels that cannot be achieved by traditional electronic ON-chip interconnects. Silicon photonics has recently emerged as a promising alternative to handle future communication needs thanks to the ultrahigh bandwidth and low power consumption. Optical networks-on-chip (ONoCs) are affected by insertion loss and crosstalk noise effects, which constrain the network scalability and impact the power consumption. This paper proposes a hybrid electronic/photonic, hybrid-topology ONoC (H2ONoC), based on a novel architecture aimed at mitigating the above effects. This paper provides a thorough description of the H2ONoC architectures as well as an experimental evaluation based on both synthetic benchmarks and real-world applications. Compared with hybrid mesh- and torus-based network-on-chip architectures, H2ONoC achieves, respectively, 13% and 18% less insertion loss, 32% and 8% less energy consumption under synthetic traffic, 74% and 14% less energy consumption with real applications, as well as better SNR when the system size scales up.

A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom

To increase the performance of chip multiprocessors, optical network-on-chip (ONoC) becomes promising because of its high bandwidth and low energy consumption. In this paper, we propose an architecture called RPNoC (Ring-based Packet-switched NoC), which uses few optical devices. Specifically, Single-waveguide RPNoC employs only one waveguide. Multiwaveguide RPNoC introduces space division multiplexing to make the architecture highly scalable. A novel wavelength assignment method and a deadlock-free deterministic routing algorithm are jointly designed, which make the network diameter quite small. This design also guarantees deadlock freedom, a little resource use, and low complexity at the same time. Evaluation is carried out for the 64-node RPNoC under different synthetic and realistic traffic patterns. The simulation result shows that it yields high throughput and low latency. Comparison with other packet-switched ONoCs shows that RPNoC has the lowest energy consumption.

Silicon-microring-based thermo-optic non-blocking four-port optical router for optical networks-on-chip

By using silicon-on-insulator platform and only four parallel-coupling one microring resonator routing elements, an active non-blocking four-port optical router was theoretically proposed for large-scale optical networks-on-chip (ONoC). Through the use of thermo-optic effect of silicon for tuning the resonance of each switching element, the router can work at 9 non-blocking routing states. Structure design and optimization were performed on the routing element at 1550 nm, and the routing topology and function were demonstrated for the four-port optical router. Detailed characterization was presented, including output spectrum, insertion loss, crosstalk, and power consumption. According to the analysis on all the data links of the router, the insertion loss is within the range of 0.13–3.36 dB, the crosstalk is <−19.46 dB, and the power consumption is within 0–88 mW. Comparison between this router and other reported four-port optical routers indicates that the proposed device uses the minimum number of rings (i.e. 4). Through using three-ring-based MRR instead of one-ring-based MRR, power consumption can be further decreased to 0–25 mW at the expense of small increased insertion loss for meeting the need of a large-scale (ONoC).

Grating-assisted vertical couplers for signal routing in multilayer integrated optical networks

Grating-assisted vertical couplers, which behave as add-drop filters, are proposed for wavelength routing of the signal among the different layers of on-chip multilayer optical networks. The device implements a 2×2 wavelength router which can be assembled into higher-order three-dimensional matrices. In particular, simple design criteria are found through a rapid and efficient optimization approach based on the mode analysis and demonstrated by the Finite Difference Time Domain (FDTD) simulations. The proposed numerical method is valid either for in-plane or for vertical grating-assisted couplers and it requires negligible computational effort. Different configurations of grating-assisted vertical couplers are designed and their spectral behavior is analyzed by the FDTD. The proposed devices achieve low values of the crosstalk between the different ports (below −20dB) and of the input reflection (below −15dB).

Network Condition-Aware Communication Mechanism for Circuit-Switched Optical Networks-on-Chips

Optical networks-on-chips (ONoCs) have emerged as a promising candidate for the future generation of multicore systems on chips. In ONoCs, an optical circuitswitching mechanism is preferred for its buffer-free mechanism. Unfortunately, blocking is a serious problem that restrains ONoCs from fully utilizing the available bandwidth. In this paper, a network condition-aware communication mechanism is proposed for circuit-switched optical networks-on-chip. The new mechanism employs a new joint metric of predicting the time and the number of blocking packets. The rules are defined according to the new metric for the setup packet, thus increasing the link utilization. Compared with previous methods, the simulation results based on synthetic traffic patterns and PARSEC benchmarks reveal that the proposed mechanism increases the efficiency of links, with higher throughput and lower endto- end latency.

Non-blocking four-port optical router based on thermooptic silicon microrings

By using silicon-on-insulator (SOI) platform, 12 channel waveguides, and four parallel-coupling one-microring resonator routing elements, a non-blocking four-port optical router is proposed. Structure design and optimization are performed on the routing elements at 1 550 nm. At drop state with a power consumption of 0 mW, the insertion loss of the drop port is less than 1.12 dB, and the crosstalk between the two output ports is less than −28 dB; at through state with a power consumption of 22 mW, the insertion loss of the through port is less than 0.45 dB, and the crosstalk between the two output ports is below −21 dB. Routing topology and function are demonstrated for the four-port optical router. The router can work at nine non-blocking routing states using the thermo-optic (TO) effect of silicon for tuning the resonance of each switching element. Detailed characterizations are presented, including output spectrum, insertion loss, and crosstalk. According to the analysis on all the data links of the router, the insertion loss is within the range of 0.13—3.36 dB, and the crosstalk is less than −19.46 dB. The router can meet the need of large-scale optical network-on-chip (ONoC).

A non-blocking wavelength routing ONoC based on two-dimension bus architecture

With the improvement of silicon-based optical devices and on-chip optical technologies, optical network-on-chip (ONoC) is becoming a significant interconnection solution for its high bandwidth, low network latency and efficient energy utilization. Some bus-based ONoCs face the problems of high bus congestion, low network utilization, which leads to high network latency and an extra overhead in power dissipation. In this paper, a non-blocking wavelength routing ONoC based on two-dimension bus architecture (2DWR-bus) is proposed to solve the problem face by previous bus-based ONoCs, realize multiple IP cores communicating with the same destination IP core simultaneously. The network simulation is carried out for the 16 cores and 64 cores ONoC under synthetic traffics. The end-to-end (ETE) delay and saturation throughput performance are evaluated and compared between 2DWR-bus and similarly-configured ONoCs. Netrace is used in the simulation to evaluate the network performance under realistic scientific application benchmarks. The insertion loss and required laser power for 2DWR-bus is calculated and made a comparison. The evaluation result shows that 2DWR-bus ONoC has better network performance when compared with other equivalent ONoCs, especially under high network offered load.

Formal Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip with WDM

Optical networks-on-chip (ONoCs) using wavelength division multiplexing (WDM) technology is one of the most promising candidates in tacking multichannel communication on the single waveguide in multicore systems-on-chip. However, compared to the traditional ONoCs with single wavelength transmitting, ONoCs employing WDM can be more susceptible to the influence of the crosstalk noise, especially the nonlinear noise generated by the four-wave mixing (FWM) effect. Consequently, the crosstalk noise can result in the signal distortion and performance degradation, even constrain the scalability of the WDM-based ONoCs. In this paper, a formal systematical analysis model including the crosstalk noise and optical signal-to-noise ratio (OSNR) analysis in mesh-based ONoCs using WDM is presented at device, router, and network levels. To demonstrate the feasibility of the proposed method, we exploit a numerical simulation example of mesh-based ONoCs using the optimized crossbar and Crux optical routers with eight optical wavelengths. The simulation results show that the crosstalk noise is the critical element for the OSNR diminution and the scalability constraint of the mesh-based ONoCs using WDM. For example, the input power is 0 dBm in the worst case, when the mesh-based WDM-based ONoCs size using optimized crossbar is 4 × 4, the average FWM noise power, linear noise power, and OSNR are –37.61 dBm, –38.86 dBm, and 4.26 dB, respectively, and these values are –37.78 dBm, –38.95 dBm, and –13.65 dB when the scale of network is 6 × 6.

STorus: A new topology for optical network-on-chip

Optical Network on Chip (ONoC) architecture is emerging as a promising candidate in multiprocessor systems-on-chip (MPSoC) because of ultrahigh communication bandwidth, low latency and power consumption. The topology and layout of ONoC has a great impact on the network performance. Waveguide crossing in the topology would influence power consumption and crosstalk noise, which could influence the size of ONoC directly. In this paper, a screwy torus topology (STorus) and a new optical router are proposed. We divide an optical network into two subnets, and connect them with gateway. The diameter of STorus is half of Torus-based ONoC and almost a quarter of Mesh-based ONoC. To reduce the number of crossing, waveguide hierarchy has been employed. The simulation results show that the new topology can improve throughput by 59.1% compared with traditional mesh under hotspot traffic, and 52.3% compared with traditional mesh under uniform traffic.

A 3D multilayer optical network on chip based on mesh topology

Optical Network-on-Chip (ONoC) is becoming a promising solution for high performance on chip interconnection, which draws much attention from many researchers. ONoC combined with 3D integration technology can address some issues of two-dimensional ONoC such as long distance and limited scalability, which have been shown to be effective solutions for further promoting the performance of ONoC. However, the infeasibility of most existing routers with four or five ports poses a problem in 3D optical interconnect as seven-port optical routers are required in 3D networks. To solve this problem, in this paper, we propose a 3D multilayer optical network on chip (3D MONoC) based on Votex, a non-blocking optical router with seven ports. We describe the optical router and the 3D network in detail. The proposed router architecture not only realizes 3D interconnection and can be utilized in most 3D ONoC, but also can be beneficial in achieving smaller area, lower cost of ONoC. We compare Votex with the traditional $$7\times 7$$7×7 optical router based on crossbar, which indicated that Votex can save cost. Moreover, we make a comparison of 3D MONoC employing Votex against its 2D counterpart. Simulation results show that the performance including ETE delay and throughput of 3D MONoC can be improved.

Lighting Up On-Chip Communications with Photonics: Design Tradeoffs for Optical NoC Architectures

Photonic on-chip interconnects are today considered a major pathway to face the insatiable performance demand of manycore computers within tight power constraints. This article provides a broad overview of the opportunities and challenges posed at the architecture level by this new interconnect paradigm. In fact, silicon Photonics introduces many new design tradeoffs, having no electronic equivalent, involving aspects such as wavelength selectivity, physical constraints, and spectral parallelism. As highlighted throughout the paper, getting a cross-cutting understanding of these tradeoffs is essential for harnessing the full potential of on-chip Photonics.