Optical Interconnection Module Research Articles

A high-density two-dimensional parallel optical interconnection module

We present a cost-effective 24-channel two-dimensional (2-D) optical interconnection module. The optical module consists of a 2-D reflective mirror with high coupling efficiency, a hot-embossed 2-D optical waveguide, a 2-D uni-ferrule, a silicon optical bench for passive alignment, and a high-speed FR-4 printed circuits board. In a transmitter-receiver link test, the fabricated module exhibited the desirable characteristics of low jitter and rise-fall times at a channel data rate of 2.5 Gb/s.

Optical interconnect modules with fully integrated reflector mirrors

A robust and cost-effective technology for integration of 45/spl deg/ reflector mirrors and polymer waveguides (WGs) into optical interconnect (OI) substrates is developed. The planar WGs are formed from photopatternable polymers with propagation losses as low as 0.05 dB/cm. The mirrors with losses of 0.5-0.8 dB are fabricated by the microdicing technique allowing lateral and vertical positioning of the mirror plane within several microns. A prototype OI module with integrated channel WGs, mirrors, and assembled connectors is fabricated and successfully tested at 10-Gb/s transmission rate.

System-level modeling and simulation of the 10G optoelectronic interconnect

Mixed-signal multidomain systems present a challenge for computer-aided design tools. Optical and electronic simulation tools are available as separate entities. However, to date, successful system-level cosimulation has not been implemented, leading to expensive refabrication. We present a unique system-level simulation tool for mixed electrooptical systems. We apply our tool Chatoyant to the simulation of an optical high-speed free-space interconnect system designed for 10-GHz speeds. The 10G free-space optical interconnect module has optical, optoelectronic, and microwave components and thus is an ideal vehicle to use as a test system. We demonstrate how Chatoyant, a mixed-signal multidomain simulator, has been used to evaluate end-to-end performance of this complex system, including the exploration of design tradeoffs and mechanical tolerancing.

Multiscale optical design for global chip-to-chip optical interconnections and misalignment tolerant packaging

As transistor densities on integrated circuits (ICs) continue to grow, off-chip bandwidth is becoming an ever-increasing performance-limiting bottleneck in systems. Electronic multichip module and printed circuit board packaging technology has not kept pace with the growth of interchip interconnection requirements. Recent advances in "smart pixel" technology offer the potential to use optical interconnects to overcome the interchip input/output bottleneck by linking dense arrays of vertical cavity surface emitting lasers and photodetectors. For optical interconnections to be relevant to real systems they must be able to be manufactured and packaged inexpensively and robustly. This paper introduces an optical design and packaging approach that utilizes multiple sizes (or scales) of optical elements to simplify the design of the optical interconnection and coupling while providing an enhanced degree of insensitivity to misalignments inherent in the packaging of these systems. The scales of the optical elements described are: the size of the IC (termed macrooptical); the size of the pitch of optical I/O (termed microoptical); and sizes in between (termed minioptical) which are smaller than the size of the IC but cover several optical I/O. This paper describes the utility of elements of each of these scales and shows that, through the combination of them, simple robust systems can be constructed. Two case studies for applying this multiscale optical design are examined. The first case study is a global chip-to-chip optical interconnection module (termed free-space accelerator for switching terabit networks) that uses a macrolens array and mirror to effect the all-to-all optical interconnection pattern among an array of ICs on a single board. Micro- and miniscale optical elements simplify the design of the macro-lens by performing corrections at scales where they are more effective. In this system, over 11 000 optical links are implemented across a five inch multichip module with diffraction limited RMS spot sizes and registration errors less than 5 /spl mu/m. The second case study analyzes designs for board-to-board optical interconnections with throw-distances ranging from one millimeter to several centimeters. In this case, micro- and miniscale optical interconnections provide insensitivity to misalignments. The results show the feasibility of an optical coupler that can tolerate the typical packaging misalignments of 5 to 10 mil without placing rigid constraints on the angular sensitivity of the modules. The multiscale optical interconnection and coupling concept is shown to provide an approach to simplifying design and packaging-and, therefore, the costs-associated with implementing optical interconnection systems.

A 36-channel parallel optical interconnect module based on optoelectronics-on-vlsi technology

We describe the packaging and testing of a two-dimensional array parallel-optics module with 36 channels with each channel operating up to 3.3 Gb/s. This represents the first commercial module based on direct integration of vertical-cavity surface-emitting lasers (VCSELs) onto silicon very large scale integration (VLSI) circuits using a hybrid optoelectronic-VLSI technology. The module eliminates wire bonds between the driver/receiver chips and the corresponding VCSELs thereby reducing crosstalk and power dissipation, simplifying packaging and alignment, and simultaneously improving bandwidth and total link jitter performance.

Two‐dimensional parallel optical interconnect module formation based on microoptical bench concept

AbstractParallel optical interconnect technology is arousing high hopes for applications to very short reaches between optical communication transmission devices and to interconnection between high‐speed computers. However, no sufficient study has been carried out on the integration technology for two‐dimensional array‐type optical components, which are indispensable for large‐scale integration of the optical components used for parallel optical interconnects. This paper presents a method of integration of parallel optical components, using the microoptical bench (MOB) proposed by the authors as an integration technique for two‐dimensional array‐type optical components, together with characteristic evaluation of the planar microlens, as the key component, and an extension of the parallel optical interconnect module using wavelength division multiplexing. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 85(7): 30–36, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10027

RHiNET‐2/SW: High‐speed network switch implemented with parallel optical interconnection for parallel computing system

AbstractWe developed the RHiNET‐2/SW high‐speed network switch for a high‐throughput parallel computing system consisting of optically interconnected distributed personal computers (PCs). RHiNET‐2/SW enables high‐throughput network switching (64 Gbit/s) by means of a switching LSI and eight pairs of synchronized parallel optical interconnection modules. To confirm the reliability of RHiNET‐2/SW, we measured its bit error rate (BER), which was less than 10−11 (estimated value: 10−20). Five RHiNET‐2/SWs and sixteen PC nodes can perform parallel computing. This result demonstrates the feasibility of optical interconnection in a high‐speed, flexible network in a parallel computing system. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 85(6): 1–10, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10022

Three-dimensional optoelectronic stacked processor by use of free-space optical interconnection and three-dimensional VLSI chip stacks.

We present a demonstration system under the three-dimensional (3D) optoelectronic stacked processor consortium. The processor combines the advantages of optics in global, high-density, high-speed parallel interconnections with the density and computational power of 3D chip stacks. In particular, a compact and scalable optoelectronic switching system with a high bandwidth is designed. The system consists of three silicon chip stacks, each integrated with a single vertical-cavity-surface-emitting-laser-metal-semiconductor-metal detector array and an optical interconnection module. Any input signal at one end stack can be switched through the central crossbar stack to any output channel on the opposite end stack. The crossbar bandwidth is designed to be 256 Gb/s. For the free-space optical interconnection, a novel folded hybrid micro-macro optical system with a concave reflection mirror has been designed. The optics module can provide a high resolution, a large field of view, a high link efficiency, and low optical cross talk. It is also symmetric and modular. Off-the-shelf macro-optical components are used. The concave reflection mirror can significantly improve the image quality and tolerate a large misalignment of the optical components, and it can also compensate for the lateral shift of the chip stacks. Scaling of the macrolens can be used to adjust the interconnection length between the chip stacks or make the system more compact. The components are easy to align, and only passive alignment is required. Optics and electronics are separated until the final assembly step, and the optomechanic module can be removed and replaced. By use of 3D chip stacks, commercially available optical components, and simple passive packaging techniques, it is possible to achieve a high-performance optoelectronic switching system.

Free-space optical interconnection modules for two-dimensional photonic very large scale integration circuitry based on microlenses and gradient-refractive-index lenses

We present different configurations for a compact free-space optical interconnection module by combining two radial gradientrefractive- index lenses and/or two arrays of refractive microlenses. Based on our findings with ray tracing and radiometric analysis, we discuss how we have selected the proper optical system configurations and how we have chosen the different design parameters to optimally accommodate different types of optoelectronic emitters such as LEDs, microcavity LEDs, and vertical-cavity surface-emitting lasers. We focused on maximizing optical coupling efficiencies and misalignment tolerances while minimizing interchannel crosstalk.

Scalability analysis of diffractive optical element-based free-space photonic circuits for interoptoelectronic chip interconnections

An interchip free-space optical interconnection module is investigated to solve the pin-input-output bottleneck at the interface of silicon integrated circuits. The scalability of the photonic circuit is theoretically analyzed by use of the minimum feature size requirement of each diffractive element used. The study showed that interconnection densities of 1000-2000 channels/cm is possible for a 40-mm interconnection length with a 3-mm-thick optical substrate. Diffraction-limited imaging capability has been demonstrated using a fabricated prototype, confirming its applicability for interchip free-space interconnections. Photonic circuit insertion losses of -23.4 dB for TE polarization and -25.9 dB for TM polarization as well as a polarization-dependent loss of 2.5 dB are found to be caused primarily by a pair of binary linear gratings used for beam deflections. Design modifications aiming at insertion loss reduction and further improvement of tolerance capabilities are also discussed.

Free-space parallel multichip interconnection system

A parallel data-communication scheme is described for interchip communication with free-space optics. We present a proof-of-concept and feasibility demonstration of a practical modular packaging approach in which free-space optical interconnect modules can be simply integrated on top of an electronic multichip module (MCM). Our packaging architecture is based on a modified folded 4-f imaging system that is implemented with off-the-shelf optics, conventional electronic packaging techniques, and passive assembly techniques to yield a potentially low-cost packaging solution. The prototype system, as built, supports 48 independent free-space channels with eight separate laser and detector chips, in which each chip consists of a one-dimensional array of 12 devices. All chips are assembled on a single ceramic carrier together with three silicon complementary metal-oxide semiconductor chips. Parallel optoelectronic (OE) free-space interconnections are demonstrated at a speed of 200 MHz. The system is compact at only 10 in.(3) (~164 cm(3)) and is scalable because it can easily accommodate additional chips as well as two-dimensional OE device arrays for increased interconnection density.

RHiNET-2/SW: a high-throughput, compact network-switch using 8.8-gbit/s optical interconnection

We have developed a high-throughput, compact network switch (the RHiNET-2/SW) for a distributed parallel computing system. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are integrated on a compact circuit board. To realize high-throughput (64 Gbit/s) and low-latency network, the SW-LSI has a customized high-speed LVDS I/O interface, and a high-speed internal SRAM memory in a 784-pin BGA one-chip package. We have also developed device implementation technologies to overcome the electrical problems (loss and crosstalk) caused by such high integration. The RHiNET-2/SW system enables high-performance parallel processing in a distributed computing environment.

Description and evaluation of the FAST-Net smart pixel-based optical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Passively aligned LD/PD array submodules by using micro-capillaries

A passive alignment technique using micro-capillaries has been developed for multichannel optical interconnection modules. The technique is applicable when coupling a four-channel LD array to a hemispherically lensed fiber array, or a four-channel PD array to a slant-polished fiber array. Alignment time was reduced to less than 1/20 that of conventional active alignment by simply positioning the fiber array through capillaries in V grooves in the Si-platform, while obtaining high coupling efficiency of -3.4/spl plusmn/0.5 dB for LD submodules and -0.4/spl plusmn/0.1 dB for PD submodules.

64-Gb/s highly reliable network switch (RHiNET-2/SW) using parallel optical interconnection

RHiNET-2/SW is a network switch that enables high-performance optical network based parallel computing system in a distributed environment. The switch used in such a computing system must provide high-speed, low-latency packet switching with high reliability. Our switch allows high-speed 8-Gb/s/port optical data transmission over a distance of up to 100 m, and the aggregate throughput is 64 Gb/s. In RHiNET-2/SW, eight pairs of 800-Mb/s/spl times/12-channel optical interconnection modules and a one-chip CMOS ASIC switch LSI (a 784-pin BGA package) are mounted on a single compact board. To enable high-performance parallel computing, this switch must provide high-speed, highly reliable node-to-node data transmission. To evaluate the reliability of the switch, we measured the bit error rate (BER) and skew between the data channels. The BER of the signal transmission through one I/O port was better than 10/sup -11/ at a data rate of 800 Mb/s /spl times/10 b with a large timing-budget margin (870 ps) and skew of less than 140 ps. This shows that RHiNET-2/SW can provide high-throughput, highly reliable optical data transmission between the nodes of a network-based parallel computing system.

Multichip free-space global optical interconnection demonstration with integrated arrays of vertical-cavity surface-emitting lasers and photodetectors

The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays of monolithically integrated vertical-cavity surface-emitting lasers (VCSEL's) and photodetectors (PD's) were designed, fabricated, and incorporated into a folded optical system that links a 10 cm x 10 cm multichip smart pixel plane to itself in a global point-to-point pattern. The optical system effects a fully connected network in which each chip is connected to all others with a multichannel bidirectional data path. VCSEL's and detectors are arranged in clusters on the chips with an interelement spacing of 140 microm. Calculations based on measurements of resolution and registration tolerances showed that the square 50-microm detector in a typical interchip link captures approximately 85% of incident light from its associated VCSEL. The measured optical transmission efficiency was 38%, with the losses primarily due to reflections at the surfaces of the multielement lenses, which were not antireflection coated for the VCSEL wavelength. The overall efficiency for this demonstration is therefore 32%. With the measured optical confinement, an optical system that is optimized for transmission at the VCSEL wavelength will achieve an overall efficiency of greater than 80%. These results suggest that, as high-density VCSEL-based smart pixel technology matures, the FAST-Net optical interconnection concept will provide a low-loss, compact, global interconnection approach for high bisection-bandwidth multiprocessor applications in switching, signal processing, and image processing.

A compact optical active connector: an optical interconnect module with an electrical connector interface

This paper describes a compact optical active connector that has both optical and electrical interfaces for an asynchronous-transfer-mode (ATM) switching system and high-speed computer network systems. This connector with an O/E or E/O conversion module can replace the conventional electrical-cable six-pin connector for an ordinary printed circuit board that has only an electrical interface. Our connector consists of a specially developed duplex MU-type submodule with photonic devices, an electrical connector, and integrated circuits (ICs). It can be used for 620-Mbps data transmission and has lower electromagnetic radiation noise than conventional connectors. Using optical active connectors to replace electrical-cable connectors will facilitate the introduction of high-throughput, large-capacity ATM switching systems, and next-generation local area network systems.

Packaging for a 40-channel parallel optical interconnection module with an over-25-Gbit/s throughput

NTT is currently working on developing a high-throughput interconnection module that is both compact and cost effective. The technology being developed is called parallel inter-board optical interconnection technology, or ParaBIT. The ParaBIT module that has been developed is the first step; it is a front-end module with 40 channels, a throughput of over 25 Gbit/s, and a transmission distance of over 100 m along multimode fibers. One major feature of this module is the use of vertical-cavity surface-emitting laser (VCSEL) arrays as very cost-effective light sources. These arrays enable the same packaging structure to be used for both the transmitter and receiver. To achieve super-multichannel performance, high-density multiport bare-fiber (BF) connectors were developed for the module's optical interface. Unlike conventional optical connectors, these BF connectors do not need a ferrule or spring. This ensures physical contact with an excellent insertion loss (less than 0.1 dB per channel). A polymeric optical waveguide film with a 45/spl deg/ mirror for coupling to the VCSEL and photo-diode (PD) arrays by passive optical alignment was also developed. To facilitate coupling between the VCSEL/PD array chips and the waveguide, a packaging technique was developed to align and die bond the optical array chips on a substrate. This technique is called transferred multichip bonding (TMB); it can be used to mount optical array chips on a substrate with a positioning error of only several micrometers. These packaging techniques enabled ultra-parallel interconnections to be achieved in prototype ParaBIT modules.

FAST-Net optical interconnection prototype demonstration

The first prototype of the free-space accelerator for switching terabit networks (FAST-Net) program is described. The optical interconnection module consists of an array of matched high-resolution, wide-angle (f/1.1) imaging lenses that effect a global point-to-point shuffle link pattern across a multichip smart pixel array. A mirror is used to fold the shuffled links back onto the array to facilitate single-plane multichip packaging and simplified opto-mechanical alignment. The test system incorporates several monolithically integrated two-dimensional arrays of vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs) in the multichip plane. In initial experiments the prototype showed good overall optical efficiency and sufficient channel separation for VCSEL/PD arrays with pitches as small as 100 m. These results suggest that high bisection bandwidth optical free-space interconnection fabrics are feasible for high-throughput switching and multiprocessor applications.

Hardware description language for optical processing (hadlop): a simulation environment for parallel optoelectronic architectures

We present a simulation environment for parallel optoelectronic data-processing systems, and we especially consider the fusion of optoelectronic integrated circuits and optical interconnection modules. hadlop, which stands for hardware description language for optical processing, is a simulator that works at the digital design level. So far, hadlop has allowed algorithm and architecture studies for smart-pixel systems. We have just begun to extend the capabilities of hadlop toward an automatic synthesis tool for three-dimensional optoelectronic VLSI circuits. A hadlop architecture will then be the basis for the automatic generation of detailed construction plans that consider the interaction between optical interconnection modules and optoelectronic integrated circuits. The simulation system is freeware and is available through the Internet at http://www2.informatik.uni-jena.de/pope/HADLOP/hadlop.html.