Abstract
An interchip free-space optical interconnection module is investigated to solve the pin-input-output bottleneck at the interface of silicon integrated circuits. The scalability of the photonic circuit is theoretically analyzed by use of the minimum feature size requirement of each diffractive element used. The study showed that interconnection densities of 1000-2000 channels/cm is possible for a 40-mm interconnection length with a 3-mm-thick optical substrate. Diffraction-limited imaging capability has been demonstrated using a fabricated prototype, confirming its applicability for interchip free-space interconnections. Photonic circuit insertion losses of -23.4 dB for TE polarization and -25.9 dB for TM polarization as well as a polarization-dependent loss of 2.5 dB are found to be caused primarily by a pair of binary linear gratings used for beam deflections. Design modifications aiming at insertion loss reduction and further improvement of tolerance capabilities are also discussed.
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