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A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

With technology advancing rapidly, the size of transistors and the distance between them is decreasing quickly. This reduction in size is causing the critical charge of sensitive nodes in SRAM cells to decrease, making them more susceptible to soft errors, especially in aerospace applications. When a radiation particle strikes a open node in a standard 6T SRAM cell, the storage data in the cell can be changed, leading to a single-event upset (SEU). To address this issue, a new Soft Error Read and write Stability improves Low Power 12T (SARP12T) SRAM cell has been introduced in this study to reduce the impact of SEUs. The performance of SARP12T has been compared to other recently developed soft-error-aware SRAM cells like QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. SARP12T is designed for the recoverability of all stored data in sensitive nodes even if they are affected by radiation strikes. Additionally, SARP12T can overcome single-event multi-node upsets (SEMNUs) that may happened at its sensitive node pair. This proposed cell also boasts the higher read stability, as the storage node holding '0' can regain from any upset during read operations. Moreover, SARP12T consumes the minimum amount of hold power, has greater write ability, and lower write delay compared to other similar cells. Despite a almost greater read delay and higher read and write energy consumption, the improvements in the proposed SARP12T cell make it a promising solution for mitigating soft errors in SRAM cells

Design of improved write and read performance 12T sram cell with leakage power control technique

Currently, memory occupies nearly eighty-five percent of the allocated chip area. Integrated electronics, such as workstations and mobile gadgets, need quick memory systems that use low power. Scaling issues make it impossible to obtain low-power and resilient SRAM cells, which are critical for Internet of Things (IoT) devices, using CMOS semiconductor technology. New nanoscale technologies, like FinFET, are being proposed as a substitute for CMOS in SRAM architecture. The study introduces a novel 12T SRAM cell design using FinFET technology, including differential writing and single-ended reading operation facilitated by write-read circuitry. The cell employs a write-assist-based approach to enhance the stability of reading and writing operations accordingly. In addition to differential writing architectures, single-ended reading decreases power use, while stacking transistors and minimizing read bit-line leakage minimizes leakage power utilization. The cell's performance has been evaluated utilizing a Cadence Spectre simulator featuring 18-nm FinFET technology and compared to current SRAM architectures at a supply voltage of 0.8 V. PVT variations are conducted to evaluate the efficiency of the suggested SRAM design. The reading and writing stability of the new SRAM cells has been enhanced by a minimum of 10 % when compared with the current counterparts. A 15 % decrease in power consumption has been seen in the suggested design compared to conventional SRAM cells of the same technology.

Modeling of Self-Aligned Selector Based on Ultra-Thin Metal Oxide for Resistive Random-Access Memory (RRAM) Crossbar Arrays.

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array.

Firefly Optimization-Based Buffer Replacement Algorithm to Improve Nand Flash Memory Performance

Because of its shock tolerance, nonvolatility, low power consumption, and fast I/O speed, flash memory is often used for storage in consumer applications and, more recently, in the business computer environment. State drives SSDs to have not-in-place updates and asymmetric I/O latency, with write/erase operations being substantially slower than read operations. In this paper, we propose a buffer replacement technique FBRA that uses the firefly algorithm (FA) to precisely predict whether the pages residing in the buffer is hot or cold. The firefly optimization estimates hot fitness value of each page in the buffer in order to accurately classify them as hot or cold by characterizing precisely the temporal and spatial locality. To increase the hit ratio and SSD buffer use, the frequently used pages should stay longer in buffer compared to other pages. The proposed approach outperforms the existing SSD buffer management strategies regarding buffer hit ratio, write count, and runtime. Trace-driven simulation is done using FlashDB Simulator to support the performance of our approach surpasses various traditional buffer replacement policies.

Firefly Optimization-Based Buffer Replacement Algorithm to Improve Nand Flash Memory Performance

Because of its shock tolerance, nonvolatility, low power consumption, and fast I/O speed, flash memory is often used for storage in consumer applications and, more recently, in the business computer environment. State drives SSDs to have not-in-place updates and asymmetric I/O latency, with write/erase operations being substantially slower than read operations. In this paper, we propose a buffer replacement technique FBRA that uses the firefly algorithm (FA) to precisely predict whether the pages residing in the buffer is hot or cold. The firefly optimization estimates hot fitness value of each page in the buffer in order to accurately classify them as hot or cold by characterizing precisely the temporal and spatial locality. To increase the hit ratio and SSD buffer use, the frequently used pages should stay longer in buffer compared to other pages. The proposed approach outperforms the existing SSD buffer management strategies regarding buffer hit ratio, write count, and runtime. Trace-driven simulation is done using FlashDB Simulator to support the performance of our approach surpasses various traditional buffer replacement policies.

Comparative analysis of query execution speed using Entity Framework for selected database engines

This article presents the comparative analysis of time efficiency while executing queries by object-relational mapping framework Entity Framework for the following database engines: Microsoft SQL Server, MySQL and PostgreSQL. Time measurements of obtaining object results from database queries were made by app created in C#. Queries referred to single or multiple tables linked by relationships (1:1, 1:n, m:n) and performed operations of reading, creating, updating and deleting data. Obtained results have been cleaned from outliers and trimmed means were given as final results. Different database engines obtained the shortest query execution times depending on record number and table structures.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read and hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21×and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99×compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States.

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state "State 1 (State 0)". Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width.

Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing.

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

Coarser Equivalences for Causal Concurrency

Trace theory (formulated by Mazurkiewicz in 1987) is a principled framework for defining equivalence relations for concurrent program runs based on a commutativity relation over the set of atomic steps taken by individual program threads. Its simplicity, elegance, and algorithmic efficiency makes it useful in many different contexts including program verification and testing. It is well-understood that the larger the equivalence classes are, the more benefits they would bring to the algorithms and applications that use them. In this paper, we study relaxations of trace equivalence with the goal of maintaining its algorithmic advantages. We first prove that the largest appropriate relaxation of trace equivalence, an equivalence relation that preserves the order of steps taken by each thread and what write operation each read operation observes, does not yield efficient algorithms. Specifically, we prove a linear space lower bound for the problem of checking, in a streaming setting, if two arbitrary steps of a concurrent program run are causally concurrent (i.e. they can be reordered in an equivalent run) or causally ordered (i.e. they always appear in the same order in all equivalent runs). The same problem can be decided in constant space for trace equivalence. Next, we propose a new commutativity-based notion of equivalence called grain equivalence that is strictly more relaxed than trace equivalence, and yet yields a constant space algorithm for the same problem. This notion of equivalence uses commutativity of grains , which are sequences of atomic steps, in addition to the standard commutativity from trace theory. We study the two distinct cases when the grains are contiguous subwords of the input program run and when they are not, formulate the precise definition of causal concurrency in each case, and show that they can be decided in constant space , despite being strict relaxations of the notion of causal concurrency based on trace equivalence.

High Tunneling Electro-Resistance Due to Resonant-Type Tunneling in a Ferroelectric Tunnel Junction (FTJ) with a Composite Barrier

Recently, ferroelectric tunnel junctions (FTJs) have emerged as potential devices for memory sector wherein the tunneling current is used to sense the direction of polarization with a nondestructive reading operation. The tunneling electro-resistance ratio (TER) is the figure of merit of this device. A composite ferroelectric-dielectric barrier is expected to achieve a high TER with enhanced performance. A theoretical modeling of a FTJ with a composite barrier (CB) consisting of a dielectric (SrTiO3) and ferroelectric (BaTiO3) layers is proposed. The potential energy profile and the transmission characteristics of a typical (20Å) SrRuO3/(20Å) SrTiO3/(20Å) BaTiO3/(12Å) Pt FTJ system were extensively studied, for both OFF and ON states. The tunneling current density and TER were computed with the variation of bias as well as with varying ferroelectric layer width. Under electric bias, an asymmetric triangular well develops at the dielectric-ferroelectric interface in its ON state whose effect in producing a resonant-type tunneling and a high tunneling current density in its ON state is explained.

Current Transformer Condition Online Monitoring Platform Based on Big Data

Abstract As an important power equipment indispensable to the normal operation of the power grid, the good or bad working condition of the current transformer directly affects the operational efficiency of the whole power grid. In this paper, an online monitoring platform based on big data technology has been developed to monitor the current status of transformers. First of all, for the temperature of the transformer, through the decoupling of the heat generation mode of the transformer, the state monitoring method based on fiber optic temperature measurement technology and optical multiplexing technology is proposed, and the overall scheme of transformer state monitoring is designed. The data signal of the transformer’s status is collected and processed, and a fault state diagnosis model is constructed based on the decision tree algorithm. Finally, according to the data requirements of the current transformer, an online monitoring platform for transformer status has been constructed using big data technology. Through the simulation test, the variation of ratio error of this paper’s monitoring method is less than 0.60%, and the variation of phase error is less than 0.75 percent, which is in line with international requirements. The average loading time of the monitoring platform is between 123.591s~143.911s, the average loading speed is less than 13s, the average throughput is between 241ops/sec ~257ops/sec, and the average latency of the read and upload operations is 24.225ms. The current transformer condition monitoring platform in this paper has good stability, the overall performance is excellent, and it provides a good solution for the research of the current transformer condition monitoring platform provides practical support for the research of current transformer condition monitoring platform.

A Multi-bit ECRAM-Based Analog Neuromorphic System with High-Precision Current Readout Achieving 97.3% Inference Accuracy.

This article proposes an analog neuromorphic system that enhances symmetry, linearity, and endurance by using a high-precision current readout circuit for multi-bit nonvolatile electro-chemical random-access memory (ECRAM). For on-chip training and inference, the system uses activation modules and matrix processing units to manage analog update/read paths and perform precise output sensing with feedback-based current scaling on the ECRAM array. The 250nm CMOS neuromorphic chip was tested with a 32 x 32 ECRAM synaptic array, achieving linear and symmetric updates and accurate read operations. The proposed circuit system updates the 32 x 32 ECRAM across 100 levels, maintaining consistent synaptic weights, and operates with an output error rate of up to 2.59% per column. It consumes 5.9 mW of power excluding the ECRAM array and achieves 97.3% inference accuracy on the MNIST dataset, close to the software-confirmed 97.78%, with only the final layer (64 x 10) mapped to the ECRAM.

SepHash: A Write-Optimized Hash Index On Disaggregated Memory via Separate Segment Structure

Disaggregated memory separates compute and memory resources into independent pools connected by fast RDMA (Remote Direct Memory Access) networks, which can improve memory utilization, reduce cost, and enable elastic scaling of compute and memory resources. Hash indexes provide high-performance single-point operations and are widely used in distributed systems and databases. However, under disaggregated memory, existing hash indexes suffer from write performance degradation due to high resize overhead and concurrency control overhead. Traditional write-optimized hash indexes are not efficient for disaggregated memory and sacrifice read performance. In this paper, we propose SepHash, a write-optimized hash index for disaggregated memory. First, SepHash proposes a two-level separate segment structure that significantly reduces the bandwidth consumption of resize operations. Second, SepHash employs a low-latency concurrency control strategy to eliminate unnecessary mutual exclusion and check overhead during insert operations. Finally, SepHash designs an efficient cache and filter to accelerate read operations. The evaluation results show that, compared to state-of-the-art distributed hash indexes, SepHash achieves a 3.3X higher write performance while maintaining comparable read performance.

Circuit-level design of radiation tolerant memory cell

As transistors shrink in size, the integration density of memory circuits like Static Random Access Memory (SRAM) cells rises, making them increasingly susceptible to Single Event Effects (SEE). In the space environment, memory circuits face stability and reliability challenges due to the presence of various charged particles such as α-particles, neutrons, electrons, heavy ions, and photons. These high-energy particles create ion tracks when they strike the memory device, leading to upsets in the storage bits. Conventional 6 T SRAM cells are susceptible to these upsets. As a solution this paper proposes a new Radiation Tolerable (RT 13 T) SRAM cell that is better suited for deep-space applications compared to other memory cell. RT13T has been validated to withstand radiation hazards through Critical Charge (QCrit) analysis, which shows that it exhibits 1.17×, 1.1×, 1.94× and 1.06× highest QCritthan QUCCE 10 T/12 T,traditional 6 T and LIOR 13 T memory cells, respectively. As the comparison made, our Proposed RT 13 T saved by5.1 %,9.9 %, 20.1 % and 7 % of the power consumption compared to QUCCE10T/12 T/LIOR 13 T/SERSC-16 T SRAM cells at a nominal supply voltage of 0.7 V. It also exhibits shorter read delay (TRA) 10.6 %, 1.34 %, 9.6 %, 22.16 %compared to QUCCE 10 T/12 T,6T, SERSC-16Tmemory cells, respectively. In terms of stability,our proposed RT13T SRAM cell exhibits 2.32×/2.05×/2.9×/1.05×/1.01 × higher read stability as compared with QUCCE10T/12 T/6T/LIOR 13 T/SERSC-16 T memory cells during the read operation. The our proposed RT13T shows improvements in design metrics are at the expense of a longer write delay. To characterize the performances of the proposed RT13T, 16-nm CMOS predictive technology model and validated through extensive simulation with licensed PrimeSim HSPICE of Synopsys. The results of our proposed RT13T cell are compared with some other previously proposed memory cells such as 6 T, QUCCE 10 T, QUCCE 12 T, LIOR 13 T and SERSC-16 T memory cells. The obtained results are tabulated and plotted for graphical analysis. In terms of area consumption our proposed 13 T consumes 0.9×/0.6 × lesser area than QUCCE 12 T/SERSC-16 T memory cells but our proposed circuit consumes 3.1×/1.08×/1.05 × more area than QUCCE10T/conventional 6 T/LIOR 13 T because QUCCE10T and 6 T consist of less number of transistors in memory cells.The cell proposed in this paper demonstrates strong radiation-hardened capabilities and excellent overall performance, making it well-suited for aerospace electronic devices and ensuring stable operation in space radiation environments.

3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure

The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR).In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells.It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1

Voice Enabled Read and Write Operation of Email System for Physically Impaired Persons

Voice Enabled Read and Write Operation of Email System for Physically Impaired Persons

Shared Memory Access Optimization Analysis System for PMIx Standard Implementation

The results in the field of system software stacks optimization for distributed computing systems based on the process management Interface (PMI) are obtained. Algorithms for synchronizing access to shared memory with a predominance of reading operations which are typical for PMIx implementation,are considered. The locking schemes N(mutex+signal) are proposed.

Cooperative management of an emission trading system: a private governance and learned auction for a blockchain approach

Although blockchain technology has received a significant amount of cutting-edge research on constructing a novel carbon trade market in theory, there is little research on using blockchain in carbon emission trading schemes (ETS). This study intends to address existing gaps in the literature by creating and simulating an ETS system based on blockchain technology. Using the ciphertext-policy attributed-based encryption algorithm and the Fabric network to build a platform may optimize the amount of data available while maintaining privacy security. Considering the augmentation of information interaction during the auction process brought about by blockchain, the learning behavior of bidding firms is introduced to investigate the impact of blockchain on ETS auction. In particular, implementing smart contracts can provide a swift and automatic settlement. The simulation results of the proposed system demonstrate the following: (1) fine-grained access is possible with a second delay; (2) the average annual compliance levels increase by 2% when bidders’ learning behavior is considered; and (3) the blockchain network can process more than 350 reading operations or 7 writing operations in a second.