Flash Memory Operations Research Articles

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

In this paper, a 3-D nand Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on nand Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line nand Flash memory application.

BPCLC: An Efficient Write Buffer Management Scheme for Flash-Based Solid State Disks

Flash memory has been widely used for storage devices in various embedded systems and enterprise computing environment, due to its shock-resistance, low power consumption, non-volatile, and high I/O speed. However, its physical characteristics impose several limitations in the design of flash-based solid state disks (SSDs). For example, its write operation costs much more time than read operation, and data in flash memory can not be overwritten before being erased. In particular, random write operations in flash memory have a very poor performance. To overcome these limitations, we propose a page-clustered LRU write buffer management scheme for flash-based SSDs, which is named BPCLC (Block Padding Cold and Large Cluster first). BPCLC adopts a new block padding technique to improve the write performance of flash-based SSDs. We conduct a trace-driven experiment and use two types of workloads to compare the performance of BPCLC with three competitors including FAB, BPLRU, and CLC. The results show that in both types of workloads, BPCLC outperforms its competitors with respect to write count, erase count, merge count, and overall I/O overhead.

Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.

Superblock FTL

In NAND flash-based storage systems, an intermediate software layer called a Flash Translation Layer (FTL) is usually employed to hide the erase-before-write characteristics of NAND flash memory. We propose a novel superblock-based FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed Superblock FTL, superblocks are mapped at coarse granularity, while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid address translation scheme has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme significantly outperforms previous block-mapped FTL schemes with roughly the same memory overhead.

플래시메모리-SSD의 인덱스 연산 성능 향상을 위한 압축된 핫-콜드 클러스터링 기법

SSD는 데스크탑 및 이동형 컴퓨터의 저장 장치를 지원하는 우수한 미디어이다. SSD는 비휘발성, 낮은 전력 소모, 빠른 데이터 접근 속도 등의 특징으로 데스크탑 및 서버용 데이터베이스의 핵심 저장 요소가 되었다. 하지만, 일반 RAM 메모리에 비하여 상대적으로 느린 연산 특성을 고려하여 기존의 전통적인 인덱스 관리 기법을 개선할 필요가 있다. 이를 위하여, 본 논문은 CHC-Tree 라고 하는 압축된 핫-콜드 클러스터링에 기반하는 새로운 인덱스 관리 기법을 제안한다. CHC-Tree는 인덱스 노드를 핫-콜드 세그먼트로 분류하며, 인덱스 노드의 키와 포인터를 압축한다. 콜드 세그먼트의 비활용노드의 오프셋 압축으로 느린 쓰기연산의 부담을 줄인다. 또한, 실험 결과를 통하여 기존의 B-Tree 기반의 인덱스 관리 기법보다 인덱스 검색 연산에서 26%, 인덱스 수정 연산에서 23% 이상 우수함을 확인하였다. SSDs are one of the best media to support portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major database storage components for desktop and server computers. However, we need to improve traditional index management schemes based on B-Tree due to the relatively slow characteristics of flash memory operations, as compared to RAM memory. In order to achieve this goal, we propose a new index management scheme based on a compressed hot-cold clustering called CHC-Tree. CHC-Tree-based index management improves index operation performance by dividing index nodes into hot or cold segments and compressing pointers and keys in the index nodes and clustering the hot or cold segments. The offset compression techniques using unused free area in cold index node lead to reduce the number of slow erase operations in index node insert/delete processes. Simulation results show that our scheme significantly reduces the write and erase operation overheads, improving the index search performance of B-Tree by up to 26 percent, and the index update performance by up to 23 percent.

Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers

Solid-state disks (SSDs) are storage devices that emulate hard drives with flash memory. They have been widely deployed in mobile computers as disk drive replacements. Flash memory is organized in terms of erase blocks. With the current technology, a block can reach the end of its lifetime after thousands of erasure operations. Wear leveling is a technique to evenly erase the entire flash memory so that all blocks remain alive as long as possible. This study introduces a new wear-leveling algorithm based the observation that, under a real-life mobile PC's workload, most erasure operations are contributed by a small fraction of blocks. Our key ideas are 1) moving rarely updated data to a block that is extraordinarily worn and 2) avoiding repeatedly involving a block in wear-leveling activities. This study presents a successful implementation of the proposed wear-leveling algorithm using about 200 bytes of RAM in an SSD controller rated at 33 MHz. Evaluation results show that this algorithm achieves even wear of the entire flash memory while reducing the overheads of extra flash-memory operations.

Pulse-agitated self-convergent programming for 4-bit per cell dual charge storage layer flash memory

A pulse-agitated (PA) self-convergent programming (SCP) scheme is proposed for 4-bit per cell vertically dual charge storage layer (DCSL) Flash memory operation in NOR-circuits. PA substrate hot electron injection (PASHEI) is used for programming, and hot hole injection (HHI) is used for erasing. Localized PASHEI enables separated data nodes, while clear electron energy modulation gives rise to accurate multi-level threshold voltage ( V th) control in the step-up potential wells of the DCSL devices. Excellent 4-bit cell reliability is maintained for the DCSL devices throughout the 10 5 programming/erasing (P/E) cycles, and inter-cell disturbances are suppressed.

Single site-controlled In(Ga)As/GaAs quantum dots: growth, properties and deviceintegration

Results obtained by an advanced growth of site-controlled quantum dots (SCQDs) onpre-patterned nanoholes and their integration into both photonic resonators andnanoelectronic memories are summarized. A specific technique has been pursuedto improve the optical quality of single SCQDs. Quantum dot (QD) layershave been vertically stacked but spectrally detuned for single SCQD studies.Thereby, the average emission linewidth of single QDs could be reduced from2.3 meV for SCQDs in a first QD layer close to the etched nanoholes down to 600 µeV in the third InAs QD layer. Accurate SCQD nucleation on large QDdistances is maintained by vertical strain induced QD coupling throughoutthe QD stacks. Record narrow linewidths of individual SCQDs down to∼110 µeV have been obtained. Experiments performed on coupled photonic SCQD–resonator devicesshow an enhancement of spontaneous emission. SCQDs have also been integrateddeterministically in high electron mobility heterostructures and flash memory operation atroom temperature has been observed.

An index management using CHC-cluster for flash memory databases

Flash memories are one of the best media to support portable and desktop computers’ storage areas. Their features include non-volatility, low power consumption, and fast access time for read operations, features which are sufficient to present flash memories as major database storage components for portable computers. However, we need to improve traditional index management schemes based on B-Tree due to the relatively slow characteristics of flash memory operations compared to RAM memory. In order to achieve this goal, we propose a new index management scheme based on a compressed hot–cold clustering called CHC-Tree. The CHC-Tree-based index management scheme improves index operation performance by compressing the flash index nodes and clustering the hot–cold segments. The cold cluster compression techniques using unused free area in index node reduces the number of slow write operations in index node insert/delete processes. Our performance evaluation shows that our scheme significantly reduces the write operation overheads, improving the index update performance of B-Tree by 21.9%.

Performance improvement of flash memories with HfOxNy∕SiO2 stack tunnel dielectrics

The operating characteristics of flash memory devices with tunnel dielectrics comprising a hafnium oxynitride (HfOxNy) layer or a hafnium oxynitride/silicon dioxide (HfOxNy∕SiO2) stack, annealed at various temperatures, were studied. The present work indicates that flash memory devices with a HfOxNy∕SiO2 stack tunnel dielectric have a higher program/erase speed and better reliability than those with a single HfOxNy layer. The stack tunnel dielectric composed of a thick HfOxNy layer and a thin SiO2 layer exhibits an even better performance in the flash memory operation. In addition, devices with HfOxNy∕SiO2 stack tunnel dielectrics annealed at 850°C show the best performance in terms of the program/erase speed, charge retention, and read disturbance.

FAB: Flash-Aware Buffer Management Policy for Portable Media Players

This paper presents a novel buffer management scheme for portable media players equipped with flash memory. Though flash memory has various advantages over magnetic disks such as small and lightweight form factor, solid-state reliability, low power consumption, and shock resistance, its physical characteristics imposes several limitations. Most notably, it takes relatively long time to write data in flash memory and the data cannot be overwritten before being erased first. Since an erase operation is performed as a unit of larger block, the employed strategy for mapping logical blocks onto physical pages affects real performance of flash memory. This article suggests a flash-aware buffer management scheme that reduces the number of erase operations by selecting a victim based on its page utilization rather than based on the traditional LRU policy. Our scheme effectively minimizes the number of write and erase operations in flash memory, reducing the total execution time by 17% compared to the LRU policy.

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.

Nanotubes in the Clean Room

The article profiles the nanotube research and development of Nantero, formed by former Harvard graduate students, whose projects may soon make their way into electronic memories. Charles M. Lieber, a major figure in nanotechnology, asked one of his graduate students in 1998 to undertake the design of a radically new type of computer memory. It would read and write digital bits with memory elements that measured less than 10 billionths of a meter (10 nanometers). Until then, the student, a German native named Thomas Rueckes, had been spending his time in Lieber's laboratory at Harvard University measuring the electrical and material properties of carbon nanotubes. Many researchers were trying to use nanotubes as wires or components in new transistor designs. Rueckes chose to focus instead on their extraordinary tensile strength and resilience. Until his graduation in 2001, Rueckes continued to develop the concept. As he worked, he realized that nanotubes had more and more to offer. They could, in theory, provide the makings of a universal memory, one that combined the speed of static random-access memory, the low cost of dynamic random-access memory (DRAM), and the nonvolatility (instant on operation) of flash memory. Its status as uber-material would also make it a low consumer of electrical power as well as resistant to potentially damaging heat, cold and magnetism. In 2001, Schmergel and Rueckes, along with Brent M. Segal, another former Harvard chemistry doctoral student, formed Nantero. When Nantero had gained confidence with the technology, it began a new round of visits to semiconductor manufacturers. In 2003 LSI Logic, a leading maker of customized chips for the telecommunications, storage and consumer electronics industries, agreed to bring the process for making what Nantero calls nanotube random-access memory (NRAM) into its factory in Gresham, Ore.

Flash [computer memory

Ever falling chip geometries are beginning to raise serious doubts as to the long-term viability of flash. Quantum tunnelling is integral to the operation of flash memory, and as chips are getting smaller the ultra-thin tunnelling barrier is becoming increasingly prone to breaking down. A second problem is with the lifetime of flash-based devices, which can be limited to around 100000 cycles. This is fine for some applications, but inadequate where data storage requirements extend over decades. Flash is also quite slow and difficult to program, two problems that are getting more significant as chip areas increase and supply voltages fall. There are three technologies looking to replace flash: magnetic RAM (MRAM), ferroelectric RAM (FRAM) and ovonic RAM. All of these use new materials to create truly nonvolatile memories with long lifetimes. Getting any one of them to replace flash in the marketplace will depend on producing a sufficiently small memory cell, while at the same time minimising the number of additional processing steps required.

20-Mb/s erase/record flash memory by asymmetrical operation

An asymmetrical recording and erasing operation of Flash memory is proposed where the threshold voltage of erase and record states are set above the thermal equilibrium threshold voltage. The recording rate is made ten times faster by using this method along with two other proposed methods: accurate control of the fastest bit and continuous recording using two memory banks. The erasing rate is also made ten times faster by using large-scale parallel operation made practical by a proposed multiphase word-driving scheme. These proposed circuit technologies will enable 20-Mb/s erase/record Flash memories for use in personal high-definition television (HDTV) movie cameras.

A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories

In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, "A double-level-V/sub th/ select gate array architecture" to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized.