Operational Transconductance Amplifier Research Articles

Simulation Based Analysis of Low-Voltage-Tunable Biquad Filter Using Operational Transconductance Amplifiers

ABSTRACT A CMOS realisation of a voltage tunable biquad filter using only MOSFET-based operational transconductance amplifier (OTA) and capacitors has been designed using silicon-based CMOS technology. It operates at a low supply voltage of 0.25 V at a 500 MHz frequency. The filter is theoretically analysed and then simulated using commercially available Cadence Virtuoso tools at 0.18 μm CMOS technology parameters. The proposed design is used to implement second-order low pass, highpass, bandpass, and bandreject filters with the same circuit simply by tuning the input voltage. The bandwidth and cut-off frequency also can be changed by changing the capacitor values.

Synthetic Transformer using Operational Transconductance Amplifier (OTA) and Voltage Differencing Current Conveyor (VDCC)

This paper presents a new realization of synthetic transformer using off the shelf active blocks. This proposed transformer is designed using operational transconductance amplifier (OTA), voltage differencing current conveyor (VDCC), resistor and capacitor. Use of VDCC helps to utilizes benefits of both voltage differencing unit and current conveyor. The working of proposed circuit is verified through simulations in LTSPICE using TSMC 180nm process characteristics. The proposed circuit offers the feature of adjusting primary and secondary self-inductances and mutual inductance independently. The bias current of the VDCC is used to control the primary and secondary self-inductance and mutual inductance of synthetic transformer.

Retraction Note: Design of three stage cascaded low power CMOS operational trans conductance amplifier (OTA) for ECG applications

Retraction Note: Design of three stage cascaded low power CMOS operational trans conductance amplifier (OTA) for ECG applications

A Modern VDCCTA Active Element and Its Electronic Application

In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS

This article presents a highly digital robust voltage-controlled oscillator (VCO)-based front end for multiplexed single-ended resistive sensor readout applications. The architecture features a modified digital phase-locked loop (DPLL) structure that enables second-order noise shaping without any operational transconductance amplifiers (OTAs) and a single feedback digital-to-analog converter (DAC). The direct conversion of the sensor input resistance to time-domain information obviates the need for any conditioning circuit, thus resulting in a highly digital and area-compact architecture. The closed loop substantially reduces the amplitude of the signal at the VCO input, thereby achieving high linearity. To ensure high robustness against supply and temperature variations, a double measurement approach is employed. Fabricated in a 180-nm CMOS process with a 0.1-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, the sensor readout consumes 109 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> of power and achieves a resolution of 96.9 dB for 0.5-ms conversion time, resulting in a Schreier figure of merit (FoM) of 166.5 dB. The circuit only requires a cheap and efficient single-point trimming calibration at room temperature. The low conversion time enables multiplexing among multiple sensor readouts. The supply and temperature sensitivities are 0.4%/V and 36 ppm/°C, respectively.

A novel voltage-mode universal second-order filter using five single ended OTAs and its quadrature sinusoidal oscillator application

This study proposes a single-ended operational trans-conductance amplifier (SEOTA)-based triple inputs and single output high-input impedance voltage-mode (VM) universal second-order filter. The proposed universal VM SEOTA-based second-order filter can be realized for the non-inverting low-pass, non-inverting high-pass, non-inverting band-reject, non-inverting all-pass and inverting band-pass filtering functions by appropriately using different triple-input voltage signals. The high-input impedances of the proposed universal VM SEOTA-based configuration enable the second-order filter to be cascaded without additional buffers. The proposed configuration does not employ external resistors and accordingly is an active SEOTAs and capacitors (SEOTA-C) universal second-order filter. The proposed circuit using two grounded capacitors which is more apposite to further develop into an integrated circuit implementation. The resonance angular frequency and quality factor are orthogonal electronically adjustable. By slightly modifying the proposed universal VM SEOTA-based second-order filter configuration, the VM SEOTA-C quadrature sinusoidal oscillator is achieved. The oscillation frequency and the oscillation condition of the quadrature sinusoidal oscillator can be independently and electronically tuned by adjusting the bias currents of two SEOTAs. PSpice simulation results confirmed theoretic anticipation. The result of the experiment of the commercially available SEOTAs, LT1228s, are also used to verify the characteristics of the proposed universal VM SEOTA-based second-order filter and VM SEOTA-based quadrature sinusoidal oscillator.

Analog Signal Processing Using Current Mode Computational Circuits

In this study, enhanced linearity and wide linear range current adder and subtractor circuits based on cascode current mirrors are presented. Among other analogue signal processing devices, the described circuits can be employed in operational transconductance amplifiers (OTA), Gm-C filters, and amplifiers. To enhance current mirroring performance, the suggested circuits use the cascode current mirror topology. A 1.8-volt supply and TSMC 0.18-micron CMOS technology were used to model the suggested circuits. The suggested circuits have an allowed error percentage of less than 2.5% and perform well in the current range of 0 to 80 A. The outcomes of the SPICE simulation have shown how well the proposed circuits work.

0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while minimizing the current consumption. Experimental measurements on prototypes implemented in a standard CMOS 180-nm technology, show superior performance as compared to the state of the art.

High-complex chaotic system based on new nonlinear function and OTA-based circuit realization

This research proposes a chaotic system using a new modified rectangular nonlinear function based on the principle of the third-order jerk concept. The dynamic behaviors can be realized by manipulating only one parameter from periodic, non-periodic, single-scroll, and double-scroll attractors. The proposed chaotic system can achieve relatively high-complexity chaotic behavior, as evident in the comparatively high Kaplan-Yorke dimension (DKY = 2.43) with the existing jerk systems. The performances of the proposed chaotic system are also computed and simulated through the MATLAB numerical analysis, including scenarios of bifurcations branches, Lyapunov exponents, route to chaos, phase portraits, 0–1 test charts, and Poincaré map. The proposed system analyzes the coexistence of asymmetric or symmetric attractors confirmed with basins of attraction to highlight the presence of multiple attractors, which influence initial conditions. In addition, the system's offset boosting and amplitude control are included. Furthermore, a double-scroll attractor and a four-scroll attractor can also be achieved by placing nonlinear functions at different positions in the third-order system., The circuits of the proposed chaotic systems can be conveniently realized using commercially available operational transconductance amplifiers (OTAs) and capacitors. The performances of the circuit are also proven through the experimental results compared with the numerical results. The experimental results exhibit the ease of construction based on the new nonlinear function and are suitable for applying in the data encryptions.

Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors

This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of pF which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor Cm along with a feed-forward capacitor Cf. The four-stage OTA uses only 500fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510ns under low quiescent power of 63.6μW for the wide range of load capacitors of 5pF to 100pF.

A 1–3 GHz CMOS mixer-first receiver frontend with dual-feedback OTA achieving 306 MHz IF bandwidth, 2.1 dB NF, and 33 dB gain

In this paper, a mixer-first receiver frontend with dual-feedback baseband is proposed. The negative resistive and positive capacitive feedback paths are both applied to single-stage inverter-based operational transconductance amplifier (OTA) with fewer poles, to cover a wide BB frequency range. The [Formula: see text]-path filtering at the RF side and second-order filtering at the BB side inhibit out-of-band blocker interferences. The receiver frontend is designed in 65 nm CMOS. Simulation results display an NF of 2.1 dB across 306 MHz IF bandwidth, and a maximum gain of 33 dB from 1 to 3 GHz LO frequency range. The in-band and out-of-band IIP3 are -13 and 16 dBm, respectively. The receiver core draws 40 mW at 1 GHz LO frequency.

Hybrid CMOS-Memristor based operational transconductance amplifier for high frequency applications

This paper deals with designing an optimized hybrid Operational Transconductance Amplifier (OTA) employing a technique called source degeneration with adaptive biasing that can be used for high frequency applications. This work targets implementation of a simple technique with less number of circuit elements which reduces the die area and power consumption and gives rise to good results. The circuit has been designed to operate with a supply voltage of ±1 V along with a bias current. The linearity which is the major drawback of the conventional Complementary Metal Oxide Semiconductor (CMOS) OTA gets improved with source degeneration technique using a non-CMOS non-volatile memory (so-called memristor). The gain-bandwidth product gets improved for an 80pF load. A biquad OTA-C filter is designed and implemented utilizing the OTA designed in this work as an application example. The realization of a high pass filter has been demonstrated. All the simulations were carried out in the Cadence® Virtuoso environment using 180 nm CMOS technology. Another facet of this paper is the memristor compatibility with the CMOS process technology.

A low-power low-noise neural recording amplifier with an improved recycling telescopic-cascode OTA

In this paper, a fully-differential low-power low-noise neural recording amplifier with a novel recycling telescopic-cascode (RTC) operational transconductance amplifier (OTA) is presented. In the proposed RTC OTA, the current recycling and cross-coupled transistors with local positive feedback are utilized to significantly improve the OTA’s parameters like small-signal DC gain and unity-gain bandwidth. The gain enhancement also improves the linearity in the closed-loop structure. Extensive analytical calculations and simulation results using TSMC 0.18-µm CMOS process are provided to examine the usefulness of the proposed OTA. The simulated neural recording amplifier achieves 3.55 µVrms input-referred noise over 1 Hz-10 kHz bandwidth with 3.03 and 1.22 noise efficiency factor for local field potential (LFP) and action potential (AP) bands, respectively. The total harmonic distortion (THD) is −41.7 dB for a 1 mVpp, 1 kHz sinusoidal input signal. The total power consumption is 1.70 µW from a single 1.8-V power supply.

A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of −109.1 dB and can deliver a maximum of 14 W into an 8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load with 93% efficiency while occupying a silicon area of 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Configurable Interface for Analog Sensor Outputs

Reading out analog sensor outputs can be a challenging task at low frequencies because of the low frequency noise. To obtain a sensor signal clearly, special interface circuits are required. By using such circuits, analog signals are cleaned from offset, drift and 1/f noise. Besides, if the interface circuitry is configurable, it can be possible to interface to inputs at different frequency ranges. At the interface block, analog sensor output signal is moved to a frequency band where low frequency noise effects are not dominant by using chopping modulation technique. The frequency-shifted signal is then filtered using various filter types. To remove the low frequency noise before moving the signal back to the original band, Gm-C filter is used. The entire topology can be configured by a 5-bit digital to analog converter (DAC) called Biasing DAC (BDAC). This allows us to digitally change the biasing current of operational transconductance amplifiers (OTA), so that OTA based amplifiers and filters can operate at different frequency ranges. As conclusion, a configurable analog sensor interface has been designed. The design and layouts have been realized and simulated in Cadence Virtuoso using UMC 130nm CMOS technology.

Design metrics for operational tran conductance amplifier

It is a highly tough undertaking to build an analogue circuit, especially one that consumes little power [1-5]. A basic component in many analogue integrated circuits like ADC, Gm-C filter and Delta Sigma modulator is the Operational Transcondactance Amplifier commonly known as the OTA. In all of these integrated circuits, the structure of the OTA is of fundamental importance. Gain Bandwidth (GBW), DC Gain, Common Mode Rejection Ratio (CMRR) and average power are performance characteristics that decide the selection of the OTA [6]. A well-designed OTA that has outstanding processing attributes such as speed, power consumption, gain and GBW is an accomplishment in itself [15]. This chapter mainly examines the performance parameters theoretically as well as analytically, which determines the design of OTA. Optimization strategies which are applicable to low voltage and low power applications, notably at the level of the transistor are also examined.

First Order Mixed Mode MOS-C All-Pass Frequency Selective Analog Network with Electronic Tuning

This work is intended to present a novel MOS-C design of first order frequency selective analog structure that plays essential role in phase equalization. The proposed idea employs 2 electronically tunable operational trans-conductance amplifiers, 7 MOS transistors forming active resistors and 1 grounded capacitor. Substantial flexibility to work in all 4 possible mode of operation enriches the uniqueness of proposed frequency selective structure. Non-ideal scenarios along with parasitic effects are also incorporated to explore real time performance of proposed structure. The emphasis on design has been enhanced by studying the effects of capacitor variations through Monte-Carlo analysis and the effects due to the temperature variations. Typical 0.18 µm CMOS process parameters are utilized in the verification of presented theoretical aspects through PSPICE simulation. To make room for the practicability of the proposed circuit, the experimental realization using commercially available ICs is also explored and included.&#x0D; HIGHLIGHTS&#x0D; &#x0D; A novel MOS-C design of first order frequency selective analog network is presented in this paper&#x0D; The proposed idea employs two electronically tunable operational trans-conductance amplifiers, seven MOS transistors forming active resistors and one grounded capacitor&#x0D; Non-ideal scenarios along with parasitic effects are also incorporated to explore real time performance of proposed structure&#x0D; 18 µm CMOS process parameters are utilized in the verification of presented theoretical aspects through PSPICE simulation&#x0D; To explore the practicability aspect of the proposed circuit, the experimental realization using commercially available ICs is also explored and included&#x0D; &#x0D; GRAPHICAL ABSTRACT

Mixed-Mode Electronically-Tunable First-Order Universal Filter Structure Employing Operational Transconductance Amplifiers

In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations.