Operational Transconductance Amplifier Research Articles

A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC 0.18μm process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ [formula omitted] z) noise and 190.47 nW micro-power for ECG applications

This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) gm enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm2 of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.

A High Gain, Low Power Operational Transconductance Amplifier Capable of Recording and Processing ECG Signals

Based on high output resistor current mirrors and differential pair inputs, a new operational transconductance amplifier (OTA) is designed in this paper that can collect, filter, denoise and amplify electrocardiogram (ECG) signals. The OTA is designed on a 0.18μm CMOS process with a supply voltage of 1.8V. In this experiment, the ECG signal generated by the human model is first simulated, which has a noise of 50 Hz from electromagnetic interference, especially the electrical power lines. The differential input pair is then connected to the model, and it is proved that it can denoise the common-mode noise. Finally, the designed OTA is connected to the manikin, and the experimental results are compared with the traditional OTA. The design achieves a differential-mode gain of 43.56dB and a common-mode gain of -31.36dB while maintaining a differential input voltage swing of 1Vpp. Experimental results show that the OTA can denoise and amplify the ECG signal without distortion.

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.

Analysis of an operational trans-conductance amplifier with positive feedback

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 μm complementary metal–oxide–semiconductor (CMOS) process.

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

A low-voltage, high-performing CMOS transistor based on multiple- output operation transconductance amplifier for current mode KHN Universal filter applications

This study proposes a current-mode KHN universal filter design that can perform three standard functions simultaneously: low-pass, high-pass, and band-pass. The circuit is built around a multiple-output operation transconductance amplifier (MO-OTA), which allows for electronically adjustable pole frequency and quality factor by modifying input bias currents (IB). The circuit layout is straightforward, with two MO-OTAs and two grounded capacitors, eliminating the need for external resistors and depending entirely on grounded components. Because of its simplicity, the circuit is suited for use in a tiny, efficient design. The proposed circuit's operation was validated using LT-Spice simulations, and the results were in line with theoretical expectations. The circuit used around 298μW of power at ±0.2V power supply voltages. These results demonstrate the circuit's potential for low-power applications, which are crucial in many modern electronic devices. The suggested current-mode KHN universal filter offers a viable option for combining various filter functions in a single circuit with customizable parameters. Its simplicity, efficiency, and performance qualities make it a feasible choice for incorporation into a variety of electronic systems, allowing for more filter design freedom.

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.

Design and Characterization of a Digitally Tunable Gm-C Filter for Multi-Standard Receivers

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals.

A novel resistorless memristor emulator circuit and its implementation of chaotic Jerk system

This work presents a novel resistorless memristor emulator circuit designed in both grounded and floating configurations. The grounded memristor consists of a Current-Controlled Current Conveyor Transconductance Amplifier (CC-CCTA) and a capacitor. On the other hand, a floating memristor includes a CC-CCTA and a capacitor, along with an additional Operational Transconductance Amplifier (OTA). These proposed emulators are electronically controllable owing to the internal structures of active elements. Theoretical analysis and simulation results have been obtained for the proposed designs. Simulation results have been conducted utilizing the LTspice program and TSMC 180 nm technology has been used for internal structures. In these results, the effects of the changing capacitor values, different frequencies, electronic tunability, reactions to temperature change, and pulse response have been investigated. Subsequently, a chaotic Jerk circuit has been implemented incorporating the proposed memristor emulator. The chaotic behavior of the floating memristor has been investigated using the LTspice simulation software.

Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

AbstractA low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain.

Adjustable resonator and anti-resonator designs for speech signal processing

Novel structures with adjustable characteristics, capable of performing the process where the vowel waveform is derived from a pulse train produced by the vibrating vocal folds and vice versa, are introduced in this work. Various design techniques are exploited to implement the required resonator and anti-resonator stages. The offered design flexibility and versatility are achieved through the employment of suitable active elements which offer electronically controlled characteristics in the resonator and anti-resonator stages, such as the Operational Transconductance Amplifiers, or through the employment of stages where their frequency behavior is digitally programmed, such as the Configurable Analog Modules included in a Field Programmable Analog Array device. The provided post-layout simulation and experimental results confirm the correct operation of the introduced structures in both the frequency and time domains.

16.2-μW Super Class-AB OTA with current-reuse technique achieving 130.3-μA/μA FoM

In this paper, a single-stage Super Class-AB operational transconductance amplifier (OTA) using current reuse technique is presented. It is based on two scaled current mirrors located at the tail current nodes of input pairs, reusing the current through the cross-coupled input pairs by a current gain factor of α, and delivering new currents to the output branch, enhancing the overall transconductance (Gm) by a factor of (1+α). With adaptive biasing and local common mode feedback (LCMFB), slew rate (SR), open loop gain (AOL) and gain-bandwidth product (GBW) are improved. An prototype has been designed in TSMC 0.18-μm CMOS process. Post-simulation shows the positive and negative slew rate of 22V/μs and −38.3V/μs, respectively, a GBW of 3.72 MHz, a DC gain of 65.6 dB with a phase margin of 69.2° for a capacitive load of 70 pF. The proposed OTA consumes a total power of 16.2 μW under a 1.8V supply voltage.

Design and Analysis of a High-Gain, Low-Noise, and Low-Power Analog Front End for Electrocardiogram Acquisition in 45 nm Technology Using gm/ID Method

In this work, an analog front-end (AFE) circuit for an electrocardiogram (ECG) detection system has been designed, implemented, and investigated in an industry-standard Cadence simulation framework using an advanced technology node of 45 nm. The AFE consists of an instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass and second-order high-pass sections), and a second-order notch filter—all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). The OTAs have been designed employing the gm/ID methodology. Both the pre-layout and post-layout simulation are carried out. The layout consumes an area of 0.00628 mm2 without the resistors and capacitors. Analysis of various simulation results are carried out for the proposed AFE. The circuit demonstrates a post-layout bandwidth of 239 Hz, with a variable gain between 44 and 58 dB, a notch depth of −56.4 dB at 50.1 Hz, a total harmonic distortion (THD) of −59.65 dB (less than 1%), an input-referred noise spectral density of <34 μVrms/Hz at the pass-band, a dynamic range of 52.71 dB, and a total power consumption of 10.88 μW with a supply of ±0.6 V. Hence, the AFE exhibits the promise of high-quality signal acquisition capability required for portable ECG detection systems in modern healthcare.

A single-IC realizable, electronically tunable, OTA-based full-wave rectifier with simultaneous positive and negative outputs

A new voltage-mode full-wave rectifier (FWR) is proposed in this study. The proposed FWR employs two single-output operational transconductance amplifiers (OTAs), four diodes, and two grounded resistors. It has high input impedance and does not need any extra bias current or voltage sources. It simultaneously provides positive and negative rectified output signals over separate output terminals. The amplitudes of both output signals can be adjusted by varying the resistor values or the transconductance (gm) values of the OTAs. It does not include any floating passive elements, so it is suitable for integrated circuit (IC) implementations. The proposed FWR can be implemented by using a single commercially available IC such as LM13700. However, the proposed FWR has a single matching condition for gm values of the OTAs. Several simulation and experimental test results are added to confirm the theory and show the operability of the proposed circuit.

A novel gain boost and slew rate enhanced CMOTA

Abstract The design of a novel current mirror operational transconductance amplifier is proposed to address the issues of low gain and limited swing rate under conditions of low voltage and power consumption. In order to improve the gain and swing rate of the amplifier, the increase and lift technology and swing rate increase technology are introduced to the traditional op-amp Simulation and verification based on 0.18 μm BCD process and candence. The results show that under 10 pF load capacitance, the gain is increased by 42 dB and the swing rate is increased by 130 times compared with the conventional transconductance op amp.

A New CMOS FTFNDITA Implementation and Its Application

ABSTRACT This research article presents a new design of a CMOS analog building block, termed a Four Terminal Floating Nullor Differential Input Transconductance Amplifier (FTFNDITA). This new analog building block can operate up to the MHz range and offers low-power dissipation circuitry. The proposed FTFNDITA works with ± 1.65 V power supply. Moreover, a ICs-based FTFNDITA is also developed using an off-self commercially available Current Feedback Operational Amplifier (CFOA) as IC AD844 and Operational Transconductance Amplifier (OTA) as IC LM13700 or IC CA3080. To extend the application perspective of the proposed FTFNDITA blocks, a few fundamental analog signal processing circuits like the design of Floating Inductor Simulator (FIS), First-Order Low-Pass Filter (FLPF), Floating Capacitance Multiplier (FCM), and its extension for active filter design, are incorporated. In addition, a non-ideality investigation is also performed to test the deviation between the ideal and practical design. Finally, PSPICE and experimental verifications are observed to validate the functionality of FTFNDITA.

1 V Tunable High-Quality Universal Filter Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of -43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology.

Design of Low Noise Low Power Instrumentation Amplifier for Biomedical Applications

Advancements in integrated circuit (IC) technology and circuit design are enabling devices to replace complex biological applications. Despite this progress, achieving necessary functionality at low power levels is crucial for fully integrated systems. Biomedical devices like pacemakers, which require ongoing battery charging, operate at nanowatt power levels over several years. To ensure long-term pacemaker survival, an Analog Front End (AFE) with low to moderate power consumption and high precision is essential. The front-end Instrumentation Amplifier (INA) is vital for signal acquisition, significantly improving the effectiveness of ECG signal collection systems.The primary aim of this research is to develop an integrated ECG instrumentation amplifier (INA) that can deliver top-notch performance while keeping noise and power consumption to a minimum. This amplifier will enable seamless monitoring of the ECG signal without interruptions. Using an AC connected Common Mode Feedback system [1]. in conjunction with an Operational Trans-conductance Amplifier (OTA) that uses a Chopper stabilization technique, the study's band pass filtering response within the ECG signal frequency range of 0-100Hz is obtained as anticipated. CMOS 45 nm technology is used throughout the entire process using Mentor Graphics EDA Tools