Pulse Width Modulation Operation Research Articles

Magnetic Saturation Suppression of Common-Mode Choke Coil by Selecting Suitable Inverter Carrier Frequency

Common-mode choke (CMC) plays an important role in suppressing the leakage current produced during the operation of pulse width modulation (PWM) inverters. However, when the common-mode path exhibits a large series stray capacitance, particularly the capacitance produced by long shielded cables, the CMC core reaches magnetic saturation. This paper presents a technique of selecting a suitable carrier frequency for the inverter to suppress the magnetic saturation of the CMC. First, the analytical approach leads to a non-saturation condition, and clarifies the maximum and minimum carrier frequency design conditions. Subsequently, the effect of the design is demonstrated by a non-linear circuit simulation and experimental tests using an actual inverter system demonstrate the effectiveness of the design technique.

A Multilevel Inverter for Instantaneous Voltage Balancing of Single Sourced Stacked DC-Link Capacitors for an Induction Motor Load

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> ” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented.

A novel unbalanced power flow analysis in active AC-DC distribution networks considering PWM convertors and distributed generations

Recent major achievements in power electronic technologies have expedited the development and proliferation of small-scale distributed generations (DGs). AC-DC distribution network creates a novel paradigm to attain the utmost benefits through smoothing the operation of different types of DGs. However, due to the asymmetrical electrifying of single-phase loads with different consumptions, variations in output power of the small-scale DGs connected to each phase, and disparate line parameters of the network, operation under unbalanced condition is inevitable. Therefore, performing AC-DC load flow analysis considering an unbalanced condition is indispensable to estimate the system states. In this paper, a novel direct approach based on backward-forward sweep (BFS) algorithm is proposed for power flow analysis in AC-DC distribution networks that applies Clarke’s transformation to model the operation of pulse width modulation (PWM) converters at unbalanced operation condition. Different control strategies including input power control (IPC), input output power control (IOPC), and output power control (OPC) are considered in the proposed formulation. Furthermore, to investigate the impacts of DGs on AC-DC distribution networks, an effective approach based on sensitivity matrix calculation is proposed to approximately update the outputs of DGs in each iteration. To evaluate the performance of the approach and examine its efficiency, the proposed formulations are applied to a hypothetical 123-bus AC-DC test system, containing different type of DGs and power converters, and compared with a heuristic method. The simulation results verify the effectiveness and applicability of the proposed method in load flow analysis of AC-DC distribution networks in unbalanced condition.

DC Bus Voltage Regulation Strategy in Maritime DC Power System for Minimized Converter Loss

In a maritime dc power system, the rectified dc-bus voltage of a permanent magnet synchronous generator is generally regulated by the pulsewidth modulation (PWM) operation of an active ac/dc converter. This article proposes a dc bus voltage regulation strategy exploiting the six-step operation. Under the six-step operation, the switching loss of the converter can be significantly reduced, compared to the PWM operation. Moreover, due to the higher modulation index and the less flux-weakening current of the six-step operation, the conduction loss can also be reduced. By employing diode rectification mode at light load, the conduction loss induced by the non-negligible ripple current of the six-step operation could be minimized. This article implements a controller for the proposed dc bus voltage regulation strategy and verifies its validity with simulation and experimental setup. According to the simulation and the experimental test, the converter efficiency at the rated load is enhanced by 0.6% and 0.4%, and the converter loss is reduced by up to 70% and 19%, respectively.

Analytical Conduction Loss Calculation of a MOSFET Three-Phase Inverter Accounting for the Reverse Conduction and the Blanking Time

The reverse conduction capability of MOSFETs is beneficial for the efficiency of a three-phase inverter. In this article, analytical expressions in closed form are presented which allow to quickly evaluate the conduction losses, considering the effect of the reverse conduction, and blanking time for both sinusoidal pulsewidth modulation operation with and without third harmonic injection. The losses of a three-phase silicon carbide MOSFET inverter suitable for traction applications are estimated with the proposed method and show good agreement of about 98.5% with measurements, performed with a calorimetric setup.

Online Monitoring of Incipient Turn Insulation Degradation for Inverter-Fed Machine Using Sensitive Tail Component in PWM Switching Oscillations

A failure of insulation is one of the main reasons for electric machine outage. Online condition monitoring (CM) of an incipient degradation of turn insulation could eliminate the potential fault at the early stage, which is attractive but challenging. To improve the sensitivity and availability of CM, a noninvasive technique is presented in this article for the inverter-fed electric machine utilizing the existing high-frequency (HF) switching oscillations during pulsewidth modulation operation. First, the tail component sensitive to turn insulation is selected among the dominant oscillation modes in switching current, which can penetrate the winding of machine within an adequate frequency band (e.g., several hundreds of kHz). Then, a noncontact and simple HF sensor is developed for switching oscillation current capture. The CM system, procedure, and turn insulation state indicator are devised. After that, experimental work is carried out on a 3-kW permanent magnet synchronous machine test rig. The results show good sensitivity (about 2%) to the local incipient degradation of turn insulation with insusceptibility to the operating conditions. Finally, further discussion is given to demonstrate the performance of the method.

Micro-LED Pixel Circuit with n-type LTPS TFTs for Pulse Width Modulation Operation

Micro-LED Pixel Circuit with n-type LTPS TFTs for Pulse Width Modulation Operation

Analysis of the Input Current-Ripple in the Series-Capacitor Boost Converter

This letter presents an analysis along with a design method and pulsewidth modulation operation for the series-capacitor boost converter, which reduces the input current ripple without increasing the stored energy in inductors, that is, without increasing their physical size. The method can also be applied to the buck version of the converter. Experimental results are provided to evaluate the performance of the proposed approach.

An Enhanced Linear Active Disturbance Rejection Rotor Position Sensorless Control for Permanent Magnet Synchronous Motors

An enhanced linear active disturbance rejection controller (ELADRC) based rotor position sensorless field-oriented control scheme for the permanent magnet synchronous motor (PMSM) drivers is proposed in this article. The ELADRC consists of two linear extended state observers (LESOs) and a proportional current controller. One LESO is designed to estimate the back electromotive force (EMF), which is treated as the external disturbance. Then, the rotor position and speed are obtained from the estimated back EMF without any phase delay or chattering problem. The other LESO is designed to estimate the internal disturbances, such as the parameter and current regulation quality variations. The estimated total disturbance is used as a feedforward compensation term in the current control loop to improve the current regulation quality of the plant, which further improves the rotor position estimation performance. The plant combined with the two LESOs is equivalent to an integrator with a unity gain, which is controlled by a simple proportional current controller to generate the desired voltage vector for the pulsewidth modulation operation. Finally, the stability of the closed-loop PMSM drive system with the ELADRC-based scheme is analyzed. Based on the analysis, the parameters of the ELADRC are designed. The proposed scheme is validated by the experimental results for a 275-W salient-pole PMSM drive in which the PMSM is similar to the traction motor used in Toyota Prius hybrid electric vehicles at a reduced scale.

Interleaved soft switching resonant converter with a small input ripple current

ABSTRACTAn interleaved frequency control soft switching converter is studied for solar power or fuel cell power applications. The proposed circuit topology contains two parallel current-fed circuit cells with interleaved pulse-width modulation operation. Thus, the ripple currents at input and output terminals are decreased. In each circuit cell, the proposed current-fed dc-dc converter includes boost circuit and resonant circuit to achieve current ripple-free on low voltage side and less switching losses on active devices. The boost circuit and the resonant circuit have same active devices to decrease power switches. Due to the resonant behaviour, the reverse recovery current loss on secondary diodes is removed. The voltage doubler circuit topology is accomplished on secondary-side to reduce diode counts and conduction loss. The performance and effectiveness of the developed interleaved PWM current-fed converter are verified and confirmed by experiments.

Control Techniques for the Back-to-Back Neutral-Point Clamped Converter in Asynchronous Operation

This paper investigates the operation of the back-to-back neutral point clamped (BTBNPC) converters when the ac voltages on both ends are asynchronous. The zero-sequence injection (ZSI) technique has been used to extend the linear modulation range of the pulsewidth modulation operation. This paper investigates the ZSI of the BTBNPC to maximize the dc-bus voltage utilization while the ac voltages of both ends have different magnitudes and phases. This study further explores the reactive current injection to reduce the risk of overmodulation when grid voltages surge. The combination of these techniques can extend the operation range of the BTBNPC over varying ac voltages of both ends with the available dc-bus voltage. In addition, the issue of the neutral-point balance is also taken into consideration. Laboratory test results are provided to verify the proposed technique.

A Simple Voltage Modulator Scheme for Torque Ripple Minimization in a Permanent Magnet Brushless DC Motor

This paper presents a simple dc-link voltage modulation scheme to minimize the commutation torque ripple in a permanent magnet brushless dc motor (PMBLdcM). Maintaining a constant current in the noncommutating (NC) phase helps to minimize the torque ripple, which can be achieved by boosting the motor input voltage whenever two phase currents are undergoing commutation. At low speeds, since the required ac voltage at commutation is also less than nominal, the standard pulsewidth modulation operation of the inverter with nominal dc-link voltage suffices. However, at higher speeds, a momentary (only during the commutation interval) boost in the dc-link voltage (above the nominal level) is needed to ensure a boost in motor voltage, and hence, a steady current in the NC phase. In the proposed scheme, the dc voltage boost at higher speeds is obtained by connecting two capacitors in series, which are normally connected in parallel, across the dc-link. The proposed scheme is verified for a 1-hp PMBLdcM drive through simulations and experiments in the laboratory. Results exhibit a notable improvement in reducing the torque ripple.

Droplet size and nozzle tip pressure from a pulse-width modulation sprayer

Pulse-width modulation (PWM) sprayers can improve application accuracy through flow control, turn compensation, and high-resolution overlap control by pulsing an electronically-actuated solenoid valve which controls the relative proportion of time each solenoid valve is open (duty cycle). The objective of this experiment was to identify the droplet size distribution and nozzle tip pressure when influenced by PWM duty cycle, nozzle technology, and gauge pressure to provide PWM guidelines. The experiment was conducted in a low-speed wind tunnel at the Pesticide Application Technology Laboratory using a SharpShooter® PWM system. In general, for non-venturi nozzles, as duty cycle decreased, droplet size slightly increased between 40 and 100% duty cycles. Conversely, venturi nozzles did not always follow this trend. The lowest duty cycle evaluated (20%) negatively impacted droplet size and caused inconsistencies for all nozzle by pressure combinations. The addition of a solenoid valve lowered nozzle tip pressure while gauge pressure remained constant indicating a restriction is present within the solenoid valve. Greater orifice sizes increased the pressure loss observed. Duty cycle minimally impacted nozzle tip pressure trends which were similar to the electrical square wave PWM signals. However, venturi nozzles deviated from this trend, specifically twin-fan, single pre-orifice venturi nozzles. In conclusion, venturi nozzles are not recommended for PWM systems as they may lead to inconsistent applications, specifically in regards to droplet size generation and nozzle tip pressures. Spray pressures of 276 kPa or greater and PWM duty cycles of 40% or greater are recommended to ensure proper PWM operation.

An Experimental Characterization for Injection Quantity of a High-pressure Injector in GDI Engines

The high-pressure (HP) injector is a highly dynamic component requiring careful voltage and pressure input modulation to achieve the required fuel injection quantities of gasoline direct injection (GDI) engines. Accurate fuel injection curves are a key influence for this technology, and therefore, will require an accurate estimation of fuel flow rate to be realized. In order to be driven to rapid response with respect to solenoid valve coils, HP injectors typically require to be designed to be capable of rapid response in GDI engines. In this paper, the design and analysis of the proposed injector drive circuit are presented. Next, the effects of total pulse width, injector supply voltage, fuel system pressure, and pulse width modulation (PWM) operation on fuel injection quantities of an HP injector are measured for achieving robust performance and stability in the presence of bounded errors of the GDI injectors due to total pulse width, injector’s supply voltage, fuel pressure and PWM operation. Additionally, the fuel injection quantities of the HP injector are measured by tuning the parameters of the injector drive circuit with the PWM operation. These are defined as the fuel injection curves. Finally, experimental results are provided for verification of the proposed injector drive circuit.

Fully Integrated Digital Average Current-Mode Control Voltage Regulator Module IC

This paper introduces a fully integrated 12-to-1.xV voltage regulator module IC. A fully synthesizable digital two-loop controller has been realized through hardware description language tools. Several new IP blocks have been developed and described in detail: a window delay-line-based analog to digital converter (DL-ADC), two independent PI compensators with shared hardware for calculations, high-resolution digital pulsewidth modulation (PWM), and a programmable dead-time module. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, all units of the digital controller have been designed through asynchronous architecture, eliminating the need of high-speed clock. High-performance synchronized, fixed frequency, PWM operation is enabled by a digital programmable time-base generator and system governor, which has been developed as well. In addition, to extend the capabilities of the window DL-ADC to support the full range of the load with minimal hardware penalty, adaptive reference of the current compensation is introduced. The mixed-signal IC has been fabricated on a 0.18- $\mu \text{m}$ 5-V CMOS process. It incorporates the digital controller and periphery as well as a synchronous buck power stage, including a drive circuitry that enables operation up to several megahertz from a 12-V input. The digital core has been realized by an automated synthesis process and place-and-route tools, resulting in an effective silicon area of 0.16 mm2. Experimental results of the fabricated IC operating in closed loop are provided, demonstrating the performance and benefits of the new controller for meeting the requirements of tight output voltage regulation over wide load range.

Circulating Resonant Current Between Integrated Half-Bridge Modules With Capacitor for Inverter Circuit Using SiC-MOSFET

This paper proposes a method to suppress the resonant current circulating between integrated half-bridge modules with phase-leg capacitors in two legs. This circuit configuration has the advantage of low stray inductance between power semiconductor devices and dc-link capacitors (phase-leg capacitors). This paper presents an analysis of the equivalent circuit for the circuit configuration that suggests that the dc-link capacitor current will increase depending on the relationship between resonant and switching frequencies. The capacitor current was experimentally evaluated under pulse-width modulation operation at switching frequencies up to 100 kHz using SiC- mosfet s. As a result, the resonant current may occur in the dc side when the resonant frequency between phase legs was close to either the fundamental or the third harmonic of the switching frequency. In order to suppress the circulating resonant current, a graphite bus bar is applied to the phase-connecting bus bar. Using the graphite bus bar, the capacitor current can be reduced by 35% without any influence from the ac-side output current.

Hybrid one‐cycle control technique for three‐phase power factor control

One-cycle control technique has been a prominent and suitable solution for improving power quality with the help of three-phase rectifiers. This study proposes a generalised control strategy for the three-phase power factor rectifier based on both the one-cycle control technique and the hybrid pulse-width modulation (PWM) strategy. Improvement of the performance while providing very low-current total harmonic distortion (THD) is achieved with the proposed scheme. Discontinuous and/or continuous PWM operation is possible with advantages of simplicity, robustness, and low cost. Simulation and experimental results confirm the feasibility of the proposed controller.

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.

Fifth- and Seventh-Order Harmonic Elimination With Multilevel Dodecagonal Voltage Space Vector Structure for IM Drive Using a Single DC Source for the Full Speed Range

This paper presents a method for generating a multilevel dodecagonal voltage space vector structure using a single dc source for induction motor drives. Multilevel dodecagonal structure combines the advantages of both multilevel and dodecagonal structures, and hence, generates low d v /d t phase voltage along with the elimination of fifth- and seventh-order harmonics over the entire modulation range. This eliminates low-order harmonic currents and prevents the generation of sixth-order torque ripple in the motor. The topology used requires only one dc source making four-quadrant operation of the drive system simpler compared to previously proposed multilevel topologies generating dodecagonal space vector structures. The topology used consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge. The FC inverter operates at a lower switching frequency and the low-order harmonics are eliminated by the switching action of the cascaded H-bridge inverter. The capacitors in the cascaded H-bridge modules are maintained at a substantially smaller voltage compared to the dc-link voltage and are inherently balanced during the pulsewidth modulation operation. This results in low switching loss, in the FC inverter as well as in the cascaded H-bridge inverter. Experimental results are included to validate the operation of the topology and modulation scheme presented in this paper.

Hybrid Electric Vehicle Motor Power Operation Control Analysis

The design of hybrid electric vehicle drive motor is based on the premise of meeting the electric requirement. As the power generation and the regenerative braking are in operation state, it can not charge the battery when the normal generating voltage of motor is lower than that of the battery. In view of the problem, the hybrid electric vehicle driving motor control system is designed. In this system, the boost operation of pulse-width modulation (PWM) method of half controlled rectifier is used to improve the power voltage, as the speed is the main measure of the feedback current and voltage. The fuzzy PID control strategy can optimize the frequency and duty cycle of PWM pulse width, and then with the generating efficiency is greatly improved. The power generation principle, control strategy and software implementation are analyzed in the paper, and its rationality is verified by experiments.