Operating System Overhead Research Articles

Introducing the explicitly many-processor approach

Abstract The deeper reasons of the present stalling in computing is scrutinized, and to enhance the single-processor performance, a new approach explicitly considering the presence of several computing units is introduced, as opposed to the presently exclusively used, 70-years old single-processor approach. The appearance of many-core processors, having many processing units in close vicinity to each other, requires to re-think some principles of computing. The goal of the approach is to enhance the single-processor performance using cooperating cores, rather than to introduce a new method for parallelization. Technically, it introduces a new control layer above the cores, a new intermediate execution unit called quasi-thread, a modified compiling method and object code for transferring parallelization information from the development system to the processor, and an on-demand self-organizing processor architecture. The resulting processors have more effective and more “green” architecture, considerably increased single-thread performance, allow for more deterministic real-time behaviour, new scheduling principles for multitasking, less operating system overhead, etc. Surprisingly, the resulting computing stack is upward compatible with the presently existing one.

Improving the Performance of CPU Architectures by Reducing the Operating System Overhead (Extended Version)

Abstract The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The major problems for real-time operating systems are determined by an excessive jitter, introduced mainly through task switching. This can alter deadline requirements, and, consequently, the predictability of hard real-time tasks. New requirements also arise for a real-time operating system used in mixed-criticality systems, when the executions of hard real-time applications require timing predictability. The present article discusses several solutions to improve the performance of CPU architectures and eventually overcome the Operating Systems overhead inconveniences. This paper focuses on the innovative CPU implementation named nMPRA-MT, designed for small real-time applications. This implementation uses the replication and remapping techniques for the program counter, general purpose registers and pipeline registers, enabling multiple threads to share a single pipeline assembly line. In order to increase predictability, the proposed architecture partially removes the hazard situation at the expense of larger execution latency per one instruction.

An experimental evaluation of IP4-IPV6 IVI translation

While IPv6 deployment in the Internet continues to grow slowly at present, the imminent exhaustion of IPv4 addresses will encourage its increased use over the next several years. However, due to the predominance of IPv4 in the Internet, the transition to IPv6 is likely to take a long time. During the transition period, translation mechanisms will enable IPv6 hosts and IPv4 hosts to communicate with each other. For example, translation can be used when a server or application works with IPv4 but not with IPv6, and the effort or cost to modify the code is large. Stateless and stateful translation is the subject of several recent IETF RFCs. We evaluate performance of the new IVI translator, which is viewed as a design for stateless translation by conducting experiments in both LAN and Internet environments using a freely available Linux implementation of IVI. To study the impact of operating system overhead on IVI translation, we implemented the IVI translator on a bare PC that runs applications without an operating system or kernel. Our results based on internal timings in each system show that translating IPv4 packets into IPv6 packets is more expensive than the reverse, and that address mapping is the most expensive IVI operation. We also measured packets per second in the LAN, roundtrip times in the LAN and Internet, IVI overhead for various prefix sizes, TCP connection time, and the delay and throughput over the Internet for various files sizes. While both the Linux and bare PC implementations of IVI have low overhead, a modest performance gain is obtained due to using a bare PC.

The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator

The high-level modeling and parameterization capabilities of current hardware description languages, as well as the huge integration capacity and flexibility provided by modern field-programmable gate arrays (FPGAs), open the way to designing processors tuned to given applications and favoring specific properties. This paper presents the Advanced Real-time Processor Architecture (ARPA)-MultiThreaded processor-a customizable, synthesizable, and time-predictable processor model optimized for multitasking real-time embedded systems, which efficiently explores modern FPGA technology. A fundamental processor component is the ARPA operating system (OS) coprocessor designed for hardware implementation of the basic real-time OS management functions, such as timing, task scheduling, synchronization and switching, efficient interrupt handling, and verification of the timing constraints. The hardware implementation of these functions allows executing them faster and more predictably, reducing the OS overhead, and improving its determinism. The performance evaluation has shown reductions of one to two orders of magnitude in the execution time of some functions of a real-time executive, in comparison with an analogous software implementation.

76 Lifestyle factors influence in the frequency in buccal micronucleus

The requirements to be fulfilled by languages in hard real-time environments, and corresponding language constructs necessitated by them, are summarised. Aimed towards enabling the production of reliable software for time-critical applications, the syntax and semantics of appropriate extensions of the high-level real-time language PEARL are described, mainly providing the following features: application oriented resource synchronisation with time-out and inherent deadlock prevention; constructs to express the exact time behaviour of tasks and to survey the occurrence and sequence of events; support of due dates observing task scheduling algorithms allowing the early detection and handling of overload conditions; accurate timing of operations; and application oriented simulation regarding the operating system overhead for software verification purposes. Finally, the operating system functions required by the proposed language elements and verification tools are outlined, and it is reported, to which extend and how they are already provided by the PEARL oriented real-time operating system PORTOS.

7 Signalling via the ALK receptor tyrosine kinase – insights from the fruitfly

The requirements to be fulfilled by languages in hard real-time environments, and corresponding language constructs necessitated by them, are summarised. Aimed towards enabling the production of reliable software for time-critical applications, the syntax and semantics of appropriate extensions of the high-level real-time language PEARL are described, mainly providing the following features: application oriented resource synchronisation with time-out and inherent deadlock prevention; constructs to express the exact time behaviour of tasks and to survey the occurrence and sequence of events; support of due dates observing task scheduling algorithms allowing the early detection and handling of overload conditions; accurate timing of operations; and application oriented simulation regarding the operating system overhead for software verification purposes. Finally, the operating system functions required by the proposed language elements and verification tools are outlined, and it is reported, to which extend and how they are already provided by the PEARL oriented real-time operating system PORTOS.

Design trade-offs for user-level I/O architectures

To address the growing I/O bottleneck, next-generation distributed I/O architectures employ scalable point-to-point interconnects and minimize operating system overhead by providing user-level access to the I/O subsystem. Reduced I/O overhead allows I/O intensive applications to efficiently employ latency hiding techniques for improved throughput. This paper presents the design of a novel scalable user-level I/O architecture and evaluates the impact of various architectural mechanisms in terms of overall performance improvement. Results demonstrate that eliminating data movement across protection domains is the dominant contributor to improved scalability. Eliminating system call and interrupt overhead only has a small additional benefit that may not justify the additional hardware support required. While this evaluation is based on one specific design, the conclusions can be generalized to other user-level I/O architectures

Interval-based analysis in embedded system design

Complex multi-processor systems-on-chip and distributed embedded systems exhibit a confusing variety of run time interdependencies. For reliable timing validation, not only application, but also architecture, scheduling and communication properties have to be considered. This is very different from functional validation, where architecture, scheduling and communication can be idealized. To avoid unknown corner-case coverage in simulation-based validation on one had, and the state-space explosion or over-simplification of unified formal performance models on the other, we take a compositional approach and combine different efficient models and methods for timing analysis of single processes, real-time operating system (RTOS) overhead, single processors and communication components, and finally multiple connected components. As a result, timing analysis of complex, heterogeneous embedded systems becomes feasible.

Stack Size Minimization for Embedded Real-Time Systems-on-a-Chip

The primary goal for real-time kernel software for single and multiple-processor on a chip systems is to support the design of timely and cost effective systems. The kernel must provide time guarantees, in order to predict the timely behaviorof the application, an extremely fast response time, in order not to waste computing power outside of the application cycles and save as much RAM space as possible in order to reduce the overall cost of the chip. The research on real-time software systems has produced algorithms that allow to effectively schedule system resources while guaranteeing the deadlines of the application and to group tasks in a very small number of non-preemptive sets which require much less RAM memory for stack. Unfortunately, up to now the research focus has been on time guarantees rather than on the optimization of RAM usage.Furthermore, these techniques do not apply to multiprocessor architectures which are likely to be widely used in future microcontrollers. This paper presents innovative scheduling and optimization algorithms that effectively solve the problem of guaranteeing schedulability with an extremely little operating system overhead and minimizing RAM usage. We developed a fast and simple algorithm for sharing resources in multiprocessor systems, together with an innovative procedure for assigning a preemption threshold to tasks. These allow the use of a single user stack. The experimental part shows the effectiveness of a simulated annealing-based tool that allows to find a schedulable system configuration starting from the selection of a near-optimal task allocation. When used in conjunction with our preemption threshold assignment algorithm, our tool further reduces the RAM usage in multiprocessor systems.

RAGS-real-analysis ALAP-guided synthesis

A new technique for single-bus heterogeneous system scheduling and hardware-software codesign is presented. This technique addresses challenging real-time problem domains (e.g., multirate periodic dependent tasks) for preemptive target systems including real-time operating system overheads and communication contention along with proper protocol handling. Such realistic system attributes are often times ignored in scheduling and codesign efforts, but are addressed here using a novel "real-analysis" approach. This technique foregoes the usual list- or cluster-oriented scheduling techniques for an as-late-as-possible (ALAP) guided iterative improvement procedure. A detailed system simulation is used at the scheduling level, which in turn is used as the core of the overall cosynthesis. Since an accurate simulation is the basis for the schedule feasibility check, separate verification steps become unnecessary. In addition to using real analysis as part of the scheduling, several other unique or unusual features are employed including the use of ALAP in heterogeneous scheduling, recursive search level at a time, allowing backtracking while maintaining polynomial execution time, as well as others. This framework appears to be unique in its ability to address the allocation/scheduling and codesign of heterogeneous systems, which, in particular, employ arbitrated buses for intertask communication.

The spring scheduling coprocessor: a scheduling accelerator

The spring scheduling coprocessor is a novel very large scale integration (VLSI) accelerator for multiprocessor real-time systems. The coprocessor can be used for static as well as online scheduling. Many different policies and their combinations can be used (e.g., earliest deadline first, highest value first, or resource-oriented policies such as earliest available time first). In this paper, we describe a coprocessor architecture, a CMOS implementation, an implementation of the host/coprocessor interface and a study of the overall performance improvement. We show that the current VLSI chip speeds up the main portion of the scheduling operation by over three orders of magnitude. We also present an overall system improvement analysis by accounting for the operating system overheads and identify the next set of bottlenecks to improve. The scheduling coprocessor includes several novel VLSI features. It is implemented as a parallel architecture for scheduling that is parameterized for different numbers of tasks, numbers of resources, and internal wordlengths. The architecture was implemented using a single-phase clocking style in several novel ways. The 328 000 transistor custom 2-/spl mu/m VLSI accelerator running with a 100-MHz clock, combined with careful hardware/software co-design results in a considerable performance improvement, thus removing a major bottleneck in real-time systems.

Software support for heterogeneous computing

As a result of advances in high-speed digital communications, researchers have begun to use collections of different high-performance machines in concert to execute computationally intensive application tasks. Existing high-performance machines typically achieve only a fraction of their peak performance on certain portions of such application programs; that is, there is a gap between average sustained performance and the machine’s peak performance. One reason for this is that different subtasks of an application can have different computational requirements that are best processed by different types of machine architectures. Thus, an important approach to high-performance computing is to construct a heterogeneous computing (HC) environment, consisting of a variety of machines interconnected by high-speed links, orchestrated to perform an application whose subtasks have diverse execution requirements. In addition to how well a subtask matches a machine, many factors must be considered to exploit optimally the power of an HC suite of machines. These include the time to move data shared by subtasks executed on different machines, the operating system overhead involved in stopping a task on one machine and restarting it on another, the ability to execute subtasks concurrently on all or some subset of the machines in the suite, and the machine and intermachine network load caused by other users of the HC system. There are many instances of successful implementations of application tasks across suites of heterogeneous machines. Typically, however, current users of HC systems must decompose the application task into appropriate subtasks themselves, decide on which machine to execute each subtask, code each subtask specifically for its target machine, and determine the relative execution schedule for the subtasks. The automation of this process is a long-term goal in the field of HC, but research conducted toward this goal should produce tools that will aid the users of HC systems until full automation is possible. Even though the field of HC is relatively new, it is very active. This paper is a brief outline of the software support challenges for HC addressed in Siegel et al. [1996], and readers interested in more details are referred to Eshaghian [1996], Freund and Siegel [1993], Freund and Sunderam [1994], Siegel et al. [1996], and Sunderam [1995]. The first step in using an HC system is to construct the application program. A programming language used in an HC environment must be compilable into efficient code for any machine in the HC suite, and the program specification should facilitate the decomposition of an application task into appropriate subtasks. One model for automated HC consists of four stages: (1) determina-

Measurement-based characterization of global memory and network contention, operating system and parallelization overheads

This study presents a characterization of (1) the global memory and interconnection network contention overhead, (2) the operating system overheads, and (3) the runtime system parallelization overheads for the Cedar shared-memory multiprocessor. The measurements were obtained using five representative compute-intensive, scientific, loop parallel applications from the Perfect Benchmark Suite. The overheads were measured for a range of Cedar configurations from 1 processor to the full 4-cluster/32-processor configuration, thus characterizing the effect of this scaling on the overheads. For the full 4-cluster Cedar, the operating system overhead was found to constitute 5--21% of the total completion time of an application. The parallelization overhead accounts for 10--25% of the application completion time, and the overhead due to global memory and network contention contributes 8--21% of the application completion time.

A camac handler for RT-11

A CAMAC handler for the RT-11 extended memory monitor is described. It permits CAMAC programs to run as virtual jobs, thus exploiting the full power of the extended memory monitor. For example, two CAMAC programs, each using its maximum 32K word virtual address space, may run in foreground/background mode. A LAM synchronized and terminated general multiple action is introduced to minimize the operating system overhead.

Additional pearl language structures for the implementation of reliable and inherently safe real-time systems

The requirements to be fulfilled by languages in hard real-time environments, and corresponding language constructs necessitated by them, are summarised. Aimed towards enabling the production of reliable software for time-critical applications, the syntax and semantics of appropriate extensions of the high-level real-time language PEARL are described, mainly providing the following features: application oriented resource synchronisation with time-out and inherent deadlock prevention; constructs to express the exact time behaviour of tasks and to survey the occurrence and sequence of events; support of due dates observing task scheduling algorithms allowing the early detection and handling of overload conditions; accurate timing of operations; and application oriented simulation regarding the operating system overhead for software verification purposes. Finally, the operating system functions required by the proposed language elements and verification tools are outlined, and it is reported, to which extend and how they are already provided by the PEARL oriented real-time operating system PORTOS.

A performance evaluation of the software-implemented fault-tolerancecomputer

The results of a performance evaluation of the Software-Implemented Fault-Tolerance (SIFT) computer system conducted in the NASA Avionics Integration Research Laboratory are presented. The essential system functions are described and compared to both earlier design proposals and subsequent design improvements. Using SIFT's specimen task load, the executive tasks, such as reconfiguration, clock synchronization, and interactive consistency, are found to consume significant computing resources. Together with other system overhead (e.g., voting and scheduling), the operating system overhead is in excess of 60%. The authors propose specific design changes that reduce this overhead burden significantly.

Incorporating System Overhead in Queuing Network Models

Multiclass queuing network models of multiprogramming computer systems are frequently used to predict the performance of computing systems as a function of user workload and hardware configuration. This paper examines three different methods for incorporating operating system overhead in multiclass queuing network models. The goal of the resultant model is to provide an accurate account of the processing performance and the system CPU overhead of each of the several different types of jobs (batch, timesharing, transaction processing, etc.) that together make up the multiprogramming workload. The first method introduces an operating sysbtm workload consisting of a fixed number of jobs to represent system CPU overhead processing. The second method extends the jobs' CPU service requests to include explicitly the CPU overhead necessary for system processing. The third method employs a communicating set of user and system job classes so that the CPU overhead can be modeled by switching jobs from user to system class whenever they require system CPU service. The capabilities and accuracy of the three methods are assessed and compared against performance and overhead data measured on a Univac 1110 computer.

Guaranteed Response Times in a Hard-Real-Time Environment

This paper describes a scheduling algorithm for a set of tasks that guarantees the time within which a task, once started, will complete. A task is started upon receipt of an external signal or the completion of other tasks. Each task has a rxed set of requirements in processor time, resources, and device operations needed for completion of its various segments. A worst case analysis of task performance is carried out. An algorithm is developed for determining the response times that can be guaranteed for a set of tasks. Operating system overhead is also accounted for.

Modular minicomputer with an associative stack and a virtual-addressing capability

The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.

Modular minicomputer with an associative stack and a virtual-addressing capability

The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.