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Abstract
Abstract The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The major problems for real-time operating systems are determined by an excessive jitter, introduced mainly through task switching. This can alter deadline requirements, and, consequently, the predictability of hard real-time tasks. New requirements also arise for a real-time operating system used in mixed-criticality systems, when the executions of hard real-time applications require timing predictability. The present article discusses several solutions to improve the performance of CPU architectures and eventually overcome the Operating Systems overhead inconveniences. This paper focuses on the innovative CPU implementation named nMPRA-MT, designed for small real-time applications. This implementation uses the replication and remapping techniques for the program counter, general purpose registers and pipeline registers, enabling multiple threads to share a single pipeline assembly line. In order to increase predictability, the proposed architecture partially removes the hazard situation at the expense of larger execution latency per one instruction.
Highlights
Nowadays, specialized CPU architectures are among the most adopted solution for obtaining high performance, especially in embedded systems
In order to obtain a competitive processor, we focus on the Multi Pipeline Register Architecture [4], [5], as a real-time operating system (RTOS) developed in hardware, based on a Hardware Scheduler Engine
This article is an extended version of the work published in [6]; in this paper, we provide a schedulability analysis of the already existing scheduling algorithms and a detailed description of the experimental results obtained during the tests performed on the nMPRA-MT CPU architecture
Summary
Nowadays, specialized CPU architectures are among the most adopted solution for obtaining high performance, especially in embedded systems. In order to meet the appropriate deadlines, a single or multi-core processor must execute multiple types of tasks, according to their priorities in different situations For this to be obtained, the fieldprogrammable gate array (FPGA) devices with a high capacity in logic gates, available today at acceptable prices, represents a hardware support for the development of embedded realtime operating systems [2], [3]. The proposed nMPRA-MT (Multi Pipeline Register Architecture – Fine-grained Multithreading) project fulfills the requirements for the time-bounded execution of parallel hard real-time tasks, being focused on multithreading execution of different types of threads. This implementation has reduced costs, the RTOS still has to be checked and validated. The validation of the proposals including the experimental results achieved during the tests, is presented in section V, while section VI concludes the paper
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