Operating Bias Conditions Research Articles

A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs

Abstract This study provides an insight into the impact of thin purely undoped GaN channel thickness (t ch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing t ch of the undoped GaN channel. We show that by decreasing t ch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing t ch. Large-signal simulations revealed an increase by 3 W mm−1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN t ch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.

Estimation of electrostatic, analogue, Linearity/RF figures-of-merit for GaN/SiC HEMT

An experimental examination of AlGaN/GaN/SiC HEMT multi-bias behaviour is presented in this paper to add to the enormous amount of device performance data in varied operating bias conditions. The study investigates various device parameters, including electrostatic performance, DC figures of merit, RF figures of merit and non-linear parameters under multi-bias conditions. The electrostatic performance is evaluated by analyzing the Ids-Vds transfer curves, ON-state and OFF-state currents, subthreshold slope and subthreshold swing. The output current, transconductance (gm), 2nd-and 3rd-order transconductance (gm2, and gm3) behaviour of the GaN device over multi-bias indicates a significant potential. The transconductance-reliant non-linear performance is assessed by analyzing voltage intercept points (VIP2 and VIP3), 3rd-order intercept point (IIP3), 1-dB compression point (1-dB CP), 3rd-order intermodulation distortion (IMD3), and total harmonic distortion (THD). In the case of RF parameters, the maximum ft and fmax values are 41 GHz and 125.7 GHz, respectively, and GBW up to 640 GHz was achieved. The relevant parameters, specifically the gain frequency product (GFP), transconductance frequency product (TFP), and the gain transconductance frequency product (GTFP), demonstrated remarkable results with maximum values of 683 GHz, 380.1 GHz/V, and 9827.7 GHz/V, respectively. These findings provide some valuable perceptions which would facilitate the fabrication of cutting-edge technologies for present and future applications.

Fully integrated FET-type gas sensor with optimized signal-to-noise ratio for H2S gas detection

The focus of gas sensor research has been on improving the response of individual sensors. However, in order to integrate sensors with CMOS circuits, a sensing system composed of an amplifier circuit with a voltage output is required. As such, in this work, we propose a novel gas sensing amplifier circuit composed of resistor- and FET-type gas sensors. Indium-gallium-zinc oxide (IGZO) is used as a sensing material for the detection of hydrogen sulfide (H2S) gas. The H2S gas sensing mechanism of the amplifier circuit is determined by the interplay between the resistor- and FET-type gas sensors. Also, the low-frequency noise characteristics of the resistor- and FET-type gas sensors are analyzed using carrier number fluctuation and Hooge’s mobility fluctuation models, respectively. The signal-to-noise ratio of the amplifier circuit is accurately characterized as a function of the input voltage. The optimal operating bias condition is proposed, and the limit of detection of the amplifier circuit is obtained under this condition. The methodology demonstrated in this work can be applied to other types of amplifier circuits, contributing to the advancement of knowledge about integrated gas sensing systems.

Understanding and Mapping Sensitivity in MoS2 Field-Effect-Transistor-Based Sensors.

Sensors based on two-dimensional (2D) field-effect transistors (FETs) are extremely sensitive and can detect charged analytes with attomolar limits of detection (LOD). Despite some impressive LODs, the operating mechanisms and factors that determine the signal-to-noise ratio in 2D FET-based sensors remain poorly understood. These uncertainties, coupled with an expansive design space for sensor layout and analyte positioning, result in a field with many reported highlights but limited collective progress. Here, we provide insight into sensing mechanisms of 2D molybdenum disulfide (MoS2) FETs by realizing precise control over the position and charge of an analyte using a customized atomic force microscope (AFM), with the AFM tip acting as an analyte. The sensitivity of the MoS2 FET channel is revealed to be nonuniform, manifesting sensitive hotspots with locations that are stable over time. When the charge of the analyte is varied, an asymmetry is observed in the device drain-current response, with analytes acting to turn the device off leading to a 2.5× increase in the signal-to-noise ratio (SNR). We developed a numerical model, applicable to all FET-based charge-detection sensors, that confirms our experimental observation and suggests an underlying mechanism. Further, extensive characterization of a set of different MoS2 FETs under various analyte conditions, coupled with the numerical model, led to the identification of three distinct SNRs that peak with dependence on the layout and operating conditions used for a sensor. These findings reveal the important role of analyte position and coverage in determining the optimal operating bias conditions for maximal sensitivity in 2D FET-based sensors, which provides key insights for future sensor design and control.

Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application.

Feasibility of ultra-sensitive 2D layered Hall elements

A Hall effect sensor is an analog transducer that detects a magnetic flux. The general requirements for its high magnetic sensitivity in conventional semiconductors are high carrier mobility and ultra-thin conduction channel in the material’s and the device’s point of view. Recently, graphene Hall elements (GHEs) that satisfy those conditions have been demonstrated with a current-normalized magnetic sensitivity (SI) superior to that of Si-based Hall sensors. Nevertheless, the feasibility of Hall elements based on an atomically thin monolayer transition metal dichalcogenide (TMD) system has not been studied thus far, although such a system would further enable a largely suppressed 2D carrier density. Herein, we show the strategy how to achieve the highest possible SI in a TMD-based Hall element in terms of the device structure as well as the operating bias condition. A monolayer molybdenum disulfide Hall element (MHE) on a hexagonal boron nitride (h-BN) thin film was fabricated, and the best bias conditions were selected based on the analytical model for zero-field transconductance data. Finally, the maximum SI of MHE/h-BN was found to be ~3000 V/AT. This work sheds light on the feasibility of TMD-based Hall element systems.

Low‐IF noise characteristics of W‐band resistive and diode mixers

ABSTRACTIn this letter, W‐band mixers (resistive and diode mixers) are designed using a 0.15 μm GaAs pseudo‐morphic high electron mobility transistor process for frequency‐modulated continuous wave radars. The measurement shows that both mixers can achieve a good conversion gain of −9 dB with high linearity performance. In addition, noise figures (NFs) of both mixers are measured especially at low intermediate frequency (IF) using a gain method. The resistive mixer exhibits 10.3–11.2 dB lower NF than the diode mixer at low IF from 100 kHz to 1 MHz. This result is also supported by the measurement of the flicker noise of HEMT and diode at each operating bias condition. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:275–278, 2017

Development of a methodology for the extraction of BSIM3v3.2.2 parameters of Ge-channel MOSFETs and estimation of analog circuit performance

We have developed an algorithm which utilizes model equations for MOSFETs to extract BSIM3v3.2.2 MOSFET model parameters of Ge-channel transistors. The model represents the entire transfer characteristics from sub-threshold to strong inversion regions and the output characteristics from linear to saturation regions thus capturing all the operating bias conditions of gate to source voltage VGS and drain to source voltage VDS. For extraction of various BSIM parameters, the model equations are fitted with reported experimental characteristics, and some with TCAD simulation data of Ge MOSFETs for various geometrical dimensions over a wide range of bias conditions. The algorithm used for extracting BSIM3V3.2.2 parameters by fitting BSIM3v3.2.2 model equations with experimental or simulation data is written in MATLAB code. The extracted BSIM model parameters are employed in ADS circuit simulator to reproduce the transfer characteristics of Ge MOSFETs with the same channel length and channel width of 80 nm for both high and low body bias conditions. The characteristics obtained from ADS match well with those obtained from TCAD simulation using SILVACOATLAS thereby ensuring the accuracy of our extraction methodology. The extracted set of BSIM3V3.2.2 parameters is used to generate transfer and output characteristics of Ge channel pMOSFETs at channel length of 70 nm. The extracted value of threshold voltage, bulk mobility and saturation velocity are −0.2 V, 0.18 m2/V.s and 1.2 × 106 m/s, respectively. Our study reveals that various device parameters such as transconductance, intrinsic voltage gain, and cut-off frequency show a maximum value of 677 μS/μm, 2.7, and 63 GHz, respectively.

Electrical and structural dependence of operating temperature of AlGaN/GaN HEMTs

Understanding the distribution of the considerable heat generated in the active region of high power AlGaN/GaN high electron mobility transistors (HEMTs) at the sub-micron length scales relevant to the failures being observed in these devices is crucial for understanding device performance and reliability. In addition, electrical bias conditions and structural characteristics such as field plates alter the electric field distribution and thermal path within the device leading to changes in the heat generation profile across the channel. This in turn influences the value and location of the device peak temperature and the channel to ambient (or case or base-plate) thermal resistance. The channel temperature distribution of AlGaN/GaN HEMT structures with and without source connected field plates were examined via micro-Raman spectroscopy and coupled electro-thermal simulation. For both type of structures, high Vds conditions lead to significantly higher channel temperature compared to that for low Vds conditions for the same power dissipation level. This is important because the industry standard Arrhenius relation assumes the total power is sufficient to describe the device channel temperature and that the bias condition is irrelevant [1]. We explore the level of agreement between modeling and experiment, and also the extent to which variability in input parameters for the modeling affects model results. We show that operating bias condition has a significant role in device reliability by altering value and location of the peak temperature, which then alters the type and rate of thermally induced degradation taking place at critical locations such as the drain side corner of the gate. Specifically, care must be taken when extrapolating results of an accelerated life test to usage conditions at dissimilar bias conditions to consider if the results will be applicable.

Multibias neural modeling of fin field‐effect transistor admittance parameters

AbstractThe goal of this study is to develop an artificial neural network (ANN) approach to model the fin field‐effect transistor (FinFET) small‐signal admittance parameters. The model is determined for the whole device as well as for the actual transistor, which is obtained after de‐embedding the effects of the probe pads, transmission lines, and substrate. The extracted model is validated in a wide range of operating bias conditions up to 50 GHz. In comparison to the earlier developed ANN‐based model of the FinFET scattering parameters, although the same accuracy is achieved, the proposed technique exhibits the main advantage of a reduced model complexity. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2082–2088, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27020

On the Electron and Hole Tunneling in a $ \hbox{HfO}_{2}$ Gate Stack With Extreme Interfacial-Layer Scaling

With decreasing SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial-layer (IL) thickness, gate currents in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dual-layer gate stacks are observed to undergo drastic changes. For an IL thickness below 3 Å, a transition from hole-current-dominated transport to electron-current-dominated transport is observed near operating bias conditions in p-channel field-effect transistors. A tunneling simulation based on the transfer-matrix approach suggests that the band offsets for the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers are reduced in the submonolayer IL regime ( <; 3 Å), promoting the transition in the conduction mechanism.

Two neural approaches for small-signal modelling of GaAs HEMTs

Focus of this paper is on the neural approach in small-signal modelling of GaAs HEMTs. Two modelling approaches based on artificial neural networks are discussed and compared. The first approach is completely based on artificial neural networks, while the second is a hybrid approach putting together artificial neural networks and an equivalent circuit representation of a microwave transistor. Both models consider the device gate width and therefore both are scalable. Results of modelling of three different AlGaAs/GaAs HEMTs in a wide range of operating bias conditions using the considered approaches are given. Different modelling aspects are discussed. A special attention is paid to the model development procedure and accuracy of the models.

Ultra Low Noise Epitaxial 4H-SiC X-Ray Detectors

The design and the experimental results of some prototypes of SiC X-ray detectors are presented. The devices have been manufactured on a 2’’ 4H-SiC wafer with 115 m thick undoped high purity epitaxial layer, which constitutes the detection’s active volume. Pad and pixel detectors based on Ni-Schottky junctions have been tested. The residual doping of the epi-layer was found to be extremely low, 3.7 x 1013 cm-3, allowing to achieve the highest detection efficiency and the lower specific capacitance of the detectors. At +22°C and in operating bias condition, the reverse current densities of the detector’s Schottky junctions have been measured to be between J=0.3 pA/cm2 and J=4 pA/cm2; these values are more than two orders of magnitude lower than those of state of the art silicon detectors. With such low leakage currents, the equivalent electronic noise of SiC pixel detectors is as low as 0.5 electrons r.m.s at room temperature, which represents a new state of the art in the scenario of semiconductor radiation detectors.

Off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.

The effects of proton irradiation on the operating voltage constraints of SiGe HBTs

The effect of proton irradiation on operating voltage constraints in SiGe HBTs is investigated for the first time in 120 GHz and 200 GHz SiGe HBTs. A variety of operating bias conditions was examined during irradiation, including terminals grounded, terminals floating, and forward active (FA) bias operation. The excess base current degradation at 5.0/spl times/10/sup 13/ p/cm/sup 2/ was similar in all cases. BV/sub CEO/ and BV/sub CBO/ showed no significant signs of degradation with irradiation. We also investigated for the first time the impact of radiation on SiGe HBTs biased under so-called "unstable" conditions (i.e., operating point instabilities). In the case of unstable bias conditions, device degradation under proton exposure is significantly different than for stable bias, and bias conditions can play a significant role in the damage process, potentially raising issues from a hardness assurance perspective.

The effects of operating bias conditions on the proton tolerance of SiGe HBTs

The effects of operating bias conditions on the proton tolerance of Silicon–Germanium (SiGe) heterojunction bipolar transistors (HBTs) are investigated for the first time. While this SiGe HBT technology is relatively insensitive to different bias conditions during radiation exposure, the cases with all terminals grounded and with the emitter–base junction reverse-biased show slightly enhanced degradation at proton fluences above 2 × 10 13 p/cm 2 compared to the other bias configurations, consistent with 2D simulations, and can thus be viewed as worst case conditions.

Semi-numerical static model for nonplanar-drift lateral DMOS transistor

A semi-numerical static model for a nonplanar-drift lateral double-diffused MOS transistor (ND-MOST) is described. The modelling methodology is based on a regional approach, and its implicit equations are solved numerically. With the support of MEDICI simulations, a simplified quasi-two-dimensional analysis is used to characterise the nonplanar-drift region. The complete model is composite and accounts for LDMOST characteristics such as the doping-graded channel, the nonplanar-drift structure, and the space-charge-limited current flow in the drift region. The model equations are continuous on all operating bias conditions, which is especially important for convergence in the circuit simulator. The model predictions are in satisfactory agreement with experimental measurements. This ND-LDMOST model is suitable for incorporation into a SPICE-like circuit simulator.

1/f noise in n- and p-channel MOS devices through irradiation and annealing

The 1/f noise of n- and p-channel MOS transistors was investigated through irradiation and biased anneals. While the increase in noise during irradiation is similar for both types of devices, the noise differs significantly in response to biased anneals. In particular, the noise decreases with decreasing Delta V/sub ot/ during positive-bias anneals in nMOS transistors but increases during positive-bias anneals for pMOS transistors. Conversely, negative bias anneals increase the noise in nMOS devices but decrease the noise in pMOS devices. These results are explained in terms of majority carrier trapping and detrapping at oxide defects near the Si/SiO/sub 2/ interface. Under normal operating bias conditions (positive bias for nMOS and negative bias for pMOS), the 1/f noise of both n- and p-channel transistors decreases through postirradiation annealing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation of Worst-Case Total Dose Radiation Effects in CMOS VLSI Circuits

A new methodology for evaluating worst-case radiation failure levels for CMOS VLSI circuits in total dose environments is presented. The new methodology reduces computation time by orders of magnitude by using simple calculations to identify vulnerable sub-circuits and worst-case irradiation and operating bias conditions. Sensitive sub-circuits are then analyzed by accurate, device-level simulators to predict radiation failure levels. The method has been implemented and results for sample circuits are described.

Radiation Hardness of CMOS LSI Circuits

Microprocessors and their associated support chips selected from commercially available types are being investigated for use in applications having radiation survival requirements. The radiation responses of advanced technology CMOS LSI devices were assessed in this study. The microprocessors tested were the RCA COSMAC CDP 1802 CD and preproduction samples of the RCA TCS 074 General Processor Unit. The memory devices tested were the Intersil 6508 and 6508A, Harris 6508-8 and RCA MWS 5001D 1K RAMs, and Intersil 6312 12K ROM. The I/O device tested was the Intersil 6402 UART. The radiation tests, in general, were performed under zero bias and also dynamic operating bias conditions provided by various "exercisers", which were designed and built to stimulate selected functional operations of the complex LSI circuits. The results of the total dose tests indicate that devices required for a microprocessor module can be selected from commercial CMOS LSI devices to provide a basic survival level of approximately 104 rad(Si). A careful selection of the CMOS ICs is mandatory since functional failure levels as low as 1,500 rad(Si) have been observed for some of the 1K RAMs. Additional experimental data presented in this paper indicate that the total-dose survival levels of systems using CMOS LSI circuits can be increased significantly if system operation is designed so that the effects of room temperature annealing, zero bias operation during irradiation, or zero bias during irradiation after a biased irradiation ("radiation annealing") can be employed.