OP 1dB Research Articles

A Compact 140-GHz, 150-mW High-Gain Power Amplifier MMIC in 250-nm InP HBT

We report here a compact 140-GHz, 150-mW high-gain solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) demonstrated in a 250-nm InP HBT technology. It utilizes five-gain stages and two-way on-chip power combining. The amplifier measures 29.5-dB mid-band $S_{21}$ gain and over 125-mW output power across 115–150-GHz operation. The peak 153-mW output power was measured at 140 GHz using only 2.7-mW RF input power—the associated large-signal gain is 17.5 dB with 9.8% power added efficiency (PAE). The 140-GHz OP1 dB 1-dB gain compression power is 106 mW with 7.0% PAE. The dc power dissipation is 1.54 W and its size is only 0.75 mm2. The 3-dB $S_{21}$ gain roll-off is between 112 and 147 GHz. The 115–150-GHz output power variation at 0-dBm input drive is only ±0.5 dB. The peak PAE varies between 8.2% and 10.5%. This D-band result improves upon by $2.3\times $ at 140 GHz the state-of-the-art peak RF power previously demonstrated by SSPA MMICs.

Ultra‐low‐LO‐power X‐band down‐conversion ring mixer using weak‐inversion biasing technique

An ultra-low-LO (local oscillator)-power X-band down-conversion ring mixer in 0.18-μm CMOS process is presented. By using the weak-inversion biasing technique, the proposed X-band ring mixer exhibits low-dc-power consumption and low-LO-drive power while maintaining a reasonable conversion gain (CG). The measurement results show that the proposed mixer demonstrates a maximum CG of 1.75 dB with ultra-low-LO-power of −8 dBm at RF of 12 GHz and IF of 100 MHz. The dc power is only 2 mW. The 3-dB RF bandwidth is from 9 to 15 GHz and the output 1-dB compression point (OP1 dB) is −14 dBm.

An $E$ -Band Analog Predistorter and Power Amplifier MMIC Chipset

An analog predistorter and power amplifier (PA) MMIC chipset has been designed to improve the overall linearity for applications in wireless communication at the $E$ -band. The circuits have been implemented in a commercial 0.1 $\mu \text{m}$ InGaAs pHEMT process. The PA delivers an output referred 1-dB gain compression (OP1 dB) of 24 dBm, saturated output power of 27 dBm, and OIP3 of 32 dBm between 71 and 76 GHz. In combination with the analog predistortion circuit, the combined chipset improves carrier to third-order intermodulation ratio by 20 dB at an average output power of 21 dBm and at the same time increasing the OP1 dB by 2 dB to 26 dBm.

A 2–22 GHz CMOS Distributed Power Amplifier With Combined Artificial Transmission Lines

This letter presents a novel compact distributed power amplifier (DPA) implemented in a 0.18-μm CMOS technology. Two three-stage DAs are combined with their input artificial transmission lines (ATLs) shared to work as a preamplifier for broadband impedance matching and gain improvement, while two four-stage DAs are combined with their output ATLs shared to work as a medium-power amplifier for high output power in a wide frequency band. Measurement results show that the DPA provides 11.9-dB average associated gain from 1 to 23.8 GHz. The output power at 1-dB output compression point (OP 1 dB ) is more than 8.9 dBm over the frequency of 2-22 GHz, and the peak power-added efficiency is 10% with the OP 1 dB of 14.5 dBm.

Linearity Enhancement of a Fully Integrated 6-GHz GaN Power Amplifier

A large-signal nonlinearity compensation technique is developed to improve the linearity of RF GaN power amplifiers. The design of a high power amplifier employing both common-source (CS) and common-gate (CG) GaN high-electron mobility transistors is presented for the IEEE 802.11p standard. The power amplifier is fabricated in 0.25- $\mu \text{m}$ GaN-on-SiC technology and occupies 1.7 mm $\times1.2$ mm. The measurements show that 35-dBm output 1-dB compression point (OP1 dB) is obtained with 39-dBm OIP3 for two-tone intermodulation distortion testing. It also achieves 31% drain efficiency at 28.8-dBm output power with 10-V supply voltage considering a more than 6-dB back-off for orthogonal frequency division multiplexing-modulated signals. Linearity enhancement by means of the proposed CS–CG configuration is demonstrated in a fully integrated GaN power amplifier at 6 GHz.

A 109 GHz CMOS Power Amplifier With 15.2 dBm Psat and 20.3 dB Gain in 65-nm CMOS Technology

This letter presents a four-stage power amplifier (PA) with four-way transformer-based current combining using a standard 65 nm CMOS process. Each stage consists of common source (CS) topology with a capacitive cross-coupling neutralization to improve power gain, reverse isolation and AM-PM distortion. The power stage uses a diode connected NMOS transistor for linearity (AM-AM nonlinearity) enhancement. The proposed PA achieves a small-signal gain of 21 dB and 3-dB bandwidth of 17 GHz, output power of 12.5 dBm at a 1 dB compression point (OP1 dB) and a saturated output power of 15.2 dBm with a peak PAE of 10.3%. The total chip size including the pads and core chip size without the pads are 0.343 mm2 and 0.103 mm2, respectively.

A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication

A peak-to-average power ratio (PAPR)-aware dual-mode power amplifier (PA) for short-range wireless communication in the subgigahertz band is proposed in this brief. By carefully choosing the bias, the dual-mode PA achieves the measured output P1 dB (OP1 dB) of 13.6 dBm with a PAE of 25.5%. Furthermore, a dynamic load modulation network is utilized to optimize the PA's efficiency at back-off power. A power-control loop is proposed to detect the input signal PAPR in real time and flexibly reconfigure the PA's operation modes. With these proposed techniques, the PAE has been improved by ×2.61 at 7-dB back-off power. The measurement shows that the subgigahertz-band PA archives an adjacent channel leakage ratio (ACLR1) of −37.3 dBc and an average/peak error vector magnitude of −30.4 dB/−20.5 dB at 8.9-dBm output power for ∼5-dB-PAPR 16-quadrature-magnitude-modulation LTE signals with 5-MHz bandwidth with the power control loop enabled. The PAPR-aware dual-mode PA, powered by a 2-V supply, occupies a 2.52-mm2 die area in a 180-nm CMOS.

X‐band SiGe bi‐complementary metal–oxide semiconductor transmit/receive module core chip for phased array RADAR applications

This study presents a transmit/receive (T/R) module core chip with 4-bit operation using 0.25 µm silicon–germanium (SiGe) bi-complementary metal–oxide semiconductor (BiCMOS) technology, for X-band phased array RADAR applications. The T/R module core chip consists of sub-blocks such as low noise amplifier, power amplifier, phase shifter, single-pole double-throw switch and variable gain amplifier. Switches incorporate n-type MOS devices while amplifiers are implemented with SiGe heterojunction bipolar transistors. Measurement results for the complete core chip and its individual sub-blocks are reported here. Between 9 and 10 GHz, the constructed T/R module achieves about 11 dB gain for both receiver (RX) and transmitter (TX) chains, while it has −10.5 dBm receiver chain third-order intermodulation intercept point (IIP3), and 16 dBm OP1 dB for transmitter chain. Root-mean-square phase error is measured as 5, whereas noise figure varies between 4 and 6 dB. The total power dissipation of core chip is about 285 mW, with a total area of 4.9 mm2.

A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications

A reconfigurable dual-mode power amplifier (PA) with an integrated transmit/receive (T/R) switch in 65-nm CMOS is presented. The PA can be reconfigured into linear mode or switching mode. In the linear mode, it achieves >19 dBm OP1 dB with >20% PAE over 0.1-1.5 GHz; in the switching mode, the maximum saturation output power of 23.2 dBm with the peak PAE of 60% is obtained. By utilizing the asymmetrical topology and stacked techniques, the T/R switch demonstrates ~0.5-dB TX insertion loss, >27-dB TX-RX isolation, and 24.8 dBm IP1 dB across 0.1-1.5 GHz. This brief proposes, for the first time, a CMOS dual-mode PA with an integrated T/R switch for multistandard applications.

Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers

A phase-delay cold-FET pre-distortion linearizer technique is proposed to improve the gain compensation ability compared with the conventional cold-FET pre-distortion linearizer. The gain expansion analysis of the power amplifier (PA) cascading with a pre-distortion linearizer and the comparison with the conventional linearizer and the proposed phase-delay linearizer are provided in this paper. To demonstrate the feasibility of this concept, a single-ended V-band cascode PA with the 90° phase-delay linearizer and a differential K-band common-source PA with the 180° phase-delay linearizer are developed to verify the characteristics. The V-band PA implemented in 90-nm CMOS process exhibits the output 1-dB compression power (OP1 dB) of 13.7 dBm and the power-added efficiency (PAE) at OP1 dB of 14.3%. The K-band PA implemented in 0.18-μm CMOS process demonstrates 17.5-dBm OP1 dB and 13.6% PAE at OP1 dB.

A high-performance CMOS power amplifier for 60 GHz short-range communication systems

A 60 GHz power amplifier for direct-conversion transceiver using standard 90 nm CMOS technology is reported.The power amplifier comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss LC power divider and combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57 ∼ 64 GHz frequency band of interest, the power amplifier consumes 44.4 mW and achieves power gain (S21) of 12.04 ± 1 dB, input-port input return loss (S11) of −6 to −9.4 dB, output-port input return loss (S22) of −10.4 to −26.4 dB, and reverse isolation (S12) of −29.2 to −30.6 dB. At 60 GHz, the power amplifier achieves Psat of 11.4 mW and maximum PAE of 15.8%. To the authors' knowledge, this is the best PAE ever reported for a 60 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1 dB) is 6 dBm at 60 GHz. These results demonstrate that the proposed power amplifier architecture is very promising for 60-GHz short-range communication systems. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1155–1160, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27522

A Single-Chip UHF RFID Reader Transceiver IC

A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900 MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The normal mode receiver in the presence of -3 dBm self-jammer achieves -75 dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25 dBm OP1 dB output power for CW. The fully-integrated fractional-N fre-quency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8 GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106 dBc/Hz@200 kHz and -131 dBc/Hz@1 MHz offset from center frequency and the integrated RMS jitter from 10 kHz to 10 MHz is less than 1.6 pS. The chip dissipates 330 mA from 3.3 V power supply when transmitting 22.4 dBm CW signal and the PAE of linear PA is up to 26%. The chip die area is 16.8 mm2.

A Highly-Integrated 3–8 GHz Ultra-Wideband RF Transmitter With Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control

This paper presents a highly-integrated 3-8 GHz ultra-wideband (UWB) RF transmitter implemented in a 1.2 V 0.13m CMOS technology. The transmitter integrates an analog baseband (PGAs and filter), an IQ modulator, a variable gain amplifier (VGA), a differential-to-single-ended amplifier, a power amplifier, as well as a transmitted signal strength indicator (TSSI). The RF VGA and the TSSI cooperate to perform an automatic transmit power control. The IQ modulator and an off-chip digital circuit implemented by a FPGA perform a carrier leakage calibration. Measured maximum output power and OP1 dB are -5 and +1.5 dBm, respectively. Measured worst carrier leakage suppression is 21 dB (before calibration) at 6.6 GHz. Measured worst sideband suppression is 29.1 dB at 7.6 GHz. The high linearity and accurate IQ modulation lead to an error vector magnitude (EVM) of -28 dB under the data rate of 480 Mb/s in WiMedia Mode 1. The entire transmitter consumes 66 mW under supply voltage of 1.2 V.

DC–20‐GHz compact SPQT switch for butler matrix switched beam smart antenna system

AbstractA DC–20‐GHz broadband and compact single‐pole‐quadruple‐throw (SPQT) switch for Butler matrix switched beam smart antenna system application has been designed and fabricated on 0.15‐μm GaAs pHEMT process. By adopting inductive high impedance transmission lines in series‐shunt switch topology, the SPQT switch demonstrates an insertion loss of 1.25–3.53 dB from DC to 20 GHz, and the isolation is higher than 22 dB with a compact chip size of 1.5 mm2. The measured output 1 dB compression point (OP1 dB) is 16 dBm at 12 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2023–2026, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26993

A 60 GHz CMOS Power Amplifier With Built-in Pre-Distortion Linearizer

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 10.72 dBm and OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB of 7.3 dBm from 1.2 V supply. After linearization, the OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

A 54–862-MHz CMOS Transceiver for TV-Band White-Space Device Applications

A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> synthesizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single-conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as well as the harmonic mixing problem in the receiver. A fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loop (PLL) with only a single LC VCO and a wideband multimodulus local oscillator (LO) generator seamlessly covers the entire band. A wideband semi-dynamic divide-by-1.5 circuit is adopted in the LO generator to reduce the VCO tuning range requirement by 25 %. A pseudoexponential capacitor bank structure in the LC VCO substantially reduces the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">step</sub> variations across the total band, which is beneficial for maintaining the PLL loop stability and dynamics over the wide band. The transceiver is implemented in 0.18-μ m CMOS, and operates with a single 1.8-V supply. The transmitter delivers a nominal output power of -3 dBm, and exhibits OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> of >; +6.4 dBm, OIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of >; +15.9 dBm, and error vector magnitude (EVM) of <; -34.7 dB for 64-QAM signal. The image and carrier leakage calibration circuits suppress the leakage components below -41 dBc across the entire band. The receiver achieves about 100-dB gain dynamic range, 3.5-6.9-dB noise figure, <; -29-dB EVM, and -43.4/-59.7-dBc third/fifth harmonic mixing suppression. The synthesizer and LO generator achieves the integrated phase noise <; 0.8 rms degree over the entire band.

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 mum pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 mum mHEMT device has a higher transconductance and cutoff frequency than a 0.15 mum pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of -7.1 dB and -0.2 dB, respectively. The pHEMT upconversion mixer has an OIP3 of -12 dBm and an OP1 dB of -24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the OIP3 and OP1 dB. Both the chip sizes are the same at 1.3 mm times 0.9 mm.

A 25–75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology

A compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm2. The OP1 dB of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to date

A Monolithic SiGe Heterojunction Bipolar Transistor Gilbert Upconverter with Inductor–Capacitor Current Mirror Load and Lumped-Element Rat-Race Balun

A 5.2 GHz upconversion Gilbert mixer with single-ended intermediate frequency (IF), local oscillator (LO), and RF ports is demonstrated using 0.35 µm SiGe heterojunction bipolar transistor (HBT) technology. The upconverter has a single-ended IF port. In addition, a lumped-element rat-race hybrid is inserted in the LO input stage to maintain balanced LO signals. The physics of the lumped-element rat-race is discussed in this paper. A passive LC current mirror is used to convert the mixer's differential outputs into a single-ended output and double the output current. The design methodology of the LC current mirror and a new approach to improve the power gain with the output buffer are developed in this paper. The fully matched Gilbert upconverter has the conversion gain of -1 dB, OP1 dB of -10 dBm and OIP3 of 6 dBm when input IF=300 MHz, LO=4.9 GHz and output RF=5.2 GHz. The LO-IF isolation is -36 dB and the LO-RF isolation is -39 dB. The supply voltage is 3.3 V, the current consumption is 11.5 mA, and the die size is 0.98×0.83 mm2 with six integrated on-chip inductors.