Operational Amplifier Research Articles

Remote sensing of H2O/HDO in the atmospheric column based on a near-infrared laser heterodyne radiometer suppressing local oscillator relative intensity noise

Laser heterodyne radiometer (LHR) exploits the heterodyne signal generated by solar radiation beated with local oscillator (LO) light to extract information on atmospheric species in the atmospheric column. Most of currently reported LHRs are affected by LO-induced relative intensity noise (RIN), which poses a challenge for high-sensitivity detection. In this work, a near-infrared RIN-suppressed LHR is proposed for simultaneous detection of water vapor and HDO in the atmospheric column. The operability of a home-made sun tracker can be obtained from coarse tracking and fine tracking, which offers an excellent opportunity for unattended observation. A tunable distributed feedback (DFB) diode laser centered at 1552.9 nm is employed as LO, where LO-induced RIN is suppressed by a semiconductor optical amplifier (SOA) operating in the dynamic gain saturation regime. By locking LO power and suppressing LO-induced RIN, the SOA-assisted LHR is dominated by 1.27 times shot-noise and the signal-to-ratio (SNR) of heterodyne signal is increased by 5 times. Based on atmospheric transmission spectra measured with the RIN-suppressed LHR in Hefei, China, the total column abundances of water vapor and HDO are retrieved to be 2050 ppm and 0.6 ppm, respectively, with uncertainty of 2 %.

A fully floating memristor emulator with long-term memory

In this paper, we proposed a fully floating memristor emulator with long-term memory characteristics. The circuit comprises operational amplifiers and an analog switch. Switching between incremental and decremental modes is easily achieved by changing the polarity of the input signal. The key feature of the emulator is its long-term memory, made possible by the switch and voltage follower. The correctness of the derived formula is verified using Matlab, and the emulator's pinched hysteresis loop and non-volatility are assessed using LTspice. Additionally, an experimental platform was constructed for physical testing, with the physical results showing consistency with the simulations. Finally, the proposed emulator was applied to a simple read-write circuit, demonstrating its practical applicability.

A novel compact and shadow resistance‐to‐frequency and resistance‐to‐time converter

AbstractThis paper presents a novel compact and shadow resistance‐to‐frequency converter and resistance‐to‐time converter. The design incorporates three current feedback operational amplifiers (CFOA) and can be implemented in CMOS technology. The design's functionality has been proven through simulation and experimental verification. The simulation and experimental findings show that the proposed design works well with small deviation between simulation and experimental results.

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.

An ultra-low power adjustable current-mode analog integrated general purpose artificial neural network classifier

This study introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The fundamental components of the architecture include current-mode circuits, representing the class, and a voltage-mode comparator. Specifically, the current mode circuits comprise the Mahalanobis distance circuit, Sigmoid function circuit, analog multiplier, and current mirrors. Regarding the voltage comparator, which receives the final decision, a folded-cascode operational amplifier is employed. The operational principles of the architecture are extensively explained and applied in a power-efficient configuration (operating under 976nW) with low power supply rails (0.6 V). The proposed implementation is tested on real-world biomedical classification tasks, achieving classification accuracy exceeding 91.6%. The designs are implemented using a 90nm CMOS process and developed using the Cadence IC Suite for both schematic and layout design. Monte-Carlo analysis, encompassing both process and mismatch, as well as corner analysis, are provided to confirm the robust characteristics of the proposed classifier. Through comparative analysis of post-layout simulation results with an equivalent software-based classifier and related literature, the proper operation of the proposed architecture is confirmed.

Fast and low power SiPM amplifier operating in a wide temperature range

The next generation of Ring Imaging CHerenkov detectors in high energy physics experiments may use SiPMs as photon sensing elements. This upgrade is necessary to achieve greater detector granularity and speed, however SiPMs need to be cooled down to cryogenic temperatures to detect single photons in high-radiation environments and avoid being overwhelmed by the presence of “dark signals”. It is therefore necessary to study and characterize SiPM models in dedicated campaigns, using a custom-built amplifying chain that can also operate in an extended temperature range, between 80 K and 300 K, for detector characterization purposes. The proposed amplifier configuration consists of two amplifying stages and achieves low jitter values (<10−20psRMS) thanks to the low electronic noise and the high amplifier bandwidth. The circuit achieves a signal bandwidth of 500MHz<BW<1GHz, a phase margin of approximately 45° and a power consumption of about 65−135mW. The amplifier prototype unit can be adjusted to cover the considered temperature range and still achieve low jitter values.

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

Analysis of an operational trans-conductance amplifier with positive feedback

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 μm complementary metal–oxide–semiconductor (CMOS) process.

Current controllers for optimizing laser cooling on cold atom experiments.

The design of a single chip current source based on a common power operational amplifier is presented and demonstrated for the purpose of controlling applied magnetic fields using bias/shim electromagnets in cold atom experiments. The efficacy of the design is realized via application to red-detuned polarization-gradient cooling of 87Rb down to 3 μK. Furthermore, we demonstrate Raman spectroscopy using these devices to apply current and so generate a precise, accurate, and reproducible magnetic field. This work is intended as a short tutorial for new graduate students and postdocs of laser cooling and trapping.

Lightning Current Measurement Method Using Rogowski Coil Based on Integral Circuit with Low-Frequency Attenuation Feedback.

A lightning current measurement method using a Rogowski coil based on an integral circuit with low-frequency attenuation feedback was proposed to address the issue of low-frequency distortion in the measurement of lightning currents on transmission lines using Rogowski coils. Firstly, the causes of low-frequency distortion in lightning current measurements using Rogowski coils were analyzed from the perspective of frequency domains. On this basis, an integration correction optimization circuit with a low-frequency attenuation feedback network was designed to correct the low-frequency distortion. The optimized integration circuit can also reduce the impact of low-frequency noise and the DC bias of the operational amplifier (op-amp) on the integration circuit due to the high low-frequency gain. Additionally, a high-pass filtering and voltage-divided sampling circuit has been added to ensure the normal operation of the integrator and improve the measurement range of the measurement system. Then, according to the relationship between the amplitude-frequency characteristics of the measurement system and the parameters of each component, the appropriate types of components and op-amp were selected to expand the measurement bandwidth. Finally, a simulation verification was conducted, and the simulation results show that this measurement method can effectively expand the lower measurement frequency limit to 20 Hz, correct the low-frequency distortion caused by Rogowski coils measuring lightning currents on transmission lines, and accurately restore the measured lightning current waveform.

A pragmatic data processing system for large resistive sensor arrays.

Large resistive sensor arrays (RSAs) show great potential in tactile perception. However, the large number of sensors can result in great hardware overhead and bring difficulties for acquiring and processing mass data timely in transient measurement applications. This paper implements a field programmable gate array (FPGA)-based data processing system for a large RSA of 96 × 96, which shows good power consumption and high-speed wireless data update. For crosstalk-free measure, the zero potential method is improved with bus switches, leading to fewer operational amplifiers required and less negative power consumption. A real-time embedded data processing system is realized by FPGA for excellent parallel processing ability. A high-speed wireless transfer scheme with automatic regulated transfer size is proposed and realized by a wireless fidelity module, which allows timely data analysis at the remote end. Moreover, fault identification of RSAs fabricated by micro-electromechanical system technology is achieved. Tests carried out on a 32 × 32 RSA show that the total power consumption is 2209 mW, including 1261 mW of processors and 948 mW of readout circuits, corresponding to 2.15 mW/pixel. The total negative power consumption of 549 mW has been reduced by 50% compared with the zero potential method. The scanning speed is 400fps, and the wireless transfer speed is up to 120fps when the transceiver and receiver are 5m apart.

Design and fabrication of S-band power amplifier for wireless sensor networks

This paper discusses the process of designing and manufacturing a wideband power amplifier operating in the S-band. To amplify a low power and broadband radio frequency signals from 2.1 GHz to 2.5 GHz, the proposed power amplifier uses a diagram of a two-stages amplification with peak offset amplification frequency 2.3 GHz. The power amplifier is designed with a center frequency difference of 2.2 GHz and 2.4 GHz respectively to achieve a bandwidth of 400 MHz. The proposed power amplifier (PA) uses RF transistor SHF-0589 using gallium arsenide heterostructure field-effect transistor (GaAs HFET) technology for high gain and low power consumption. The complete amplifier achieves power gain 21.1 dB inband 2.1-2.5 GHz and achieve maximum power gain of 22.5 dB at the frequency of 2.4 GHz; the output power rise up to 33 dBm; input reflection coefficient (S11) reaches -19.2 dB and output reflection coefficient reaches -17.2 dB. The designed amplifier circuit can be used for wireless sensor networks operating at S-band.

A multiplexed sensing system with multimodal readout electronics and thread-based electrochemical sensors for high throughput screening

High throughput screening (HTS) based on microwell (or bioreactor) arrays is a well-established approach for rapid screening and identification of lead molecules or target analytes for drug discovery and other applications in biotechnology. However, it has been challenging to scale up these platforms due to the lack of integrated sensors to monitor the microenvironment of each microwell in the array needed. In this work, we present a practical solution for a miniaturized multiplexed sensing system with integrated circuitry capable of performing continuous electrochemical potentiometric and amperometric measurements. The platform uses lightweight multiplexed electrochemical sensors implemented on thin textile threads, all of which share a single operational amplifier (op-amp) and a switch network for both voltage and current measurements. The resulting platform forgoes the need for large-area sensors or bulky multichannel potentiostat with a simple readout circuitry capable of multimodal measurements. The design and validation of the multiplexed sensing system have been reported in the context of measuring pH and oxygen (O2), which are crucial biomarkers for any HTS application. The thread-based pH and O2 sensors possess sensitivities of ∼65.87 mV/pH for the pH sensor (n = 3) and 0.6621 nA/mg L-1 for the O2 sensor (n = 3). This architecture is modular such that it can be easily extended to monitoring multiple biomarkers employing thread-based sensors and sharing the same readout circuitry, making it a practical and versatile tool for biotechnology research.

Towards scalable cryogenic quantum dot biasing using memristor-based DC sources

Cryogenic memristor-based DC sources offer a promising avenue for in situ biasing of quantum dot arrays. In this study, we present experimental results and discuss the scaling potential for such DC sources. We first demonstrate the operation of a commercial discrete operational amplifier down to ▪ which is used on the DC source prototype. Then, the tunability of the memristor-based DC source is validated by performing several ▪-DC sweeps with a resolution of ▪ at room temperature and at ▪. Additionally, the DC source prototype exhibits a limited output drift of ▪ at ▪. This showcases the potential of memristor-based DC sources for quantum dot biasing. Limitations in power consumption and voltage resolution using discrete components highlight the need for a fully integrated and scalable complementary metal–oxide–semiconductor-based (CMOS-based) approach. To address this, we propose to monolithically co-integrate emerging non-volatile memories (eNVMs) and ▪ CMOS circuitry. Simulations reveal a reduction in power consumption, down to ▪ per DC source and in footprint. This allows for the integration of up to one million eNVM-based DC sources at the ▪ stage of a dilution fridge, paving the way for near term large-scale quantum computing applications.

A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation

This paper presents a high-precision, low-power bandgap voltage reference with a 3.0 V output voltage suitable for battery-management systems. Compared to Brokaw's type bandgap references (BGRs), Cross-connected NPN transistors facilitate higher output voltages without the necessity of operational amplifiers and are unaffected by the current-mirror mismatch. Base-current compensation is proposed to address the effect of base current on voltage output temperature characteristics at low power consumption. A piecewise exponential curvature correction stains high-order compensation for the nonlinear characteristic of base-emitter voltage. Experimental results of the proposed BGR implemented in a 0.18-μm Bipolar-CMOS-DMOS (BCD) process demonstrate that the temperature coefficient is 2.23 ppm/°C over the range of −40 °C–120 °C. The line regulation is 0.2 mV/V at a 5–6 V supply voltage with a supply current of only 4.2 μA. The die area of the fabricated BGR is 0.105 mm2.

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.

A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

AbstractAnalog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.

Operational Amplifiers Defect Detection and Localization Using Digital Injectors and Observer Circuits

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage, as well as performing defect localization in these circuits, has proven to be a difficult/expensive task, even with sophisticated testing circuitry. The ISO 26262 standard for functional safety (FuSa) includes the stringent requirement that an automotive IC must have a very high defect coverage. This reinforces the need to ensure the functionality of analog and mixed (AMS) circuits, especially in mission critical applications. This paper presents an all-digital op amp defect detection, diagnosis, and localization method that can be used both for production and in-field tests and discusses various implementation of the proposed method. We validated our results using extensive transistor-level simulations of multiple op amp architectures using TSMC 180 nm technology. Across op amp architectures and multiple implementation approaches, we achieved a worst-case and best-case defect coverage of 94.5% and 99%, respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

Design and Characterization of a Digitally Tunable Gm-C Filter for Multi-Standard Receivers

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals.

An ICMR-enhanced three-opamp instrumentation amplifier

The three-operational amplifiers (three-opamp) structure is a widely used topology to design precision instrumentation amplifiers (IAs). However, the input common-mode range (ICMR) of the classical three-opamp IA is limited to the output voltage range of the internal operational amplifiers, resulting in the output voltage range being constrained by the input common-mode voltage. This article proposes an ICMR-enhanced three-opamp topology, which constructs a common-mode feedback (CMFB) loop at the first stage of the IA, enabling the first stage has the capability of common-mode rejection. Hence, the proposed ICMR-enhanced three-opamp IA overcomes the limitation of ICMR, eliminates the constraint of the output voltage range and improves the common-mode rejection ratio (CMRR). The proposed circuit was designed and simulated using complementary bipolar process. The simulation results showed that the output voltage range remains constant regardless of the input common-mode voltages, the CMRR is greater than 150 dB, and the Gain Bandwidth Product (GBW) was 4.1 MHz. The advantages of the proposed ICMR-enhanced three-opamp IA will enable its use in more environments.