Op-amp Circuit Research Articles

The Design of Low Power Op-amp for Biomedical Application

This work presents a low-power operational amplifier (op-amp) circuit design which optimized and tailored specifically for biomedical circuit application in low power environment. The proposed op-amp design incorporates the folded cascode differential amplifier technique with a low voltage supply 1.2 V, utilizing current biasing, current mirrors, and adopted low-power circuit topologies. AC and DC analysis are carried out to analyse the performance of the proposed design. Extensive simulations executed using industrial standard EDA tool have validated the circuit design, and demonstrated a gain of 70.94 dB, UGBW of 4.90 MHz, GM of 52.70 dB, PM of 82.02 degrees, PSRR of 82.77 dB, CMRR of 100.78 dB, and total power dissipation of only 28.07 mW. Low power consumption is essential for biomedical circuit applications, and the result shows a significant power reduction without compromising other performance parameters. The proposed op-amp circuit design is suitable to be implemented in low-power and high-performance biomedical devices.

An Exploration into the Fault Diagnosis of Analog Circuits Using Enhanced Golden Eagle Optimized 1D-Convolutional Neural Network (CNN) with a Time-Frequency Domain Input and Attention Mechanism.

With the continuous operation of analog circuits, the component degradation problem gradually comes to the forefront, which may lead to problems, such as circuit performance degradation, system stability reductions, and signal quality degradation, which could be particularly evident in increasingly complex electronic systems. At the same time, due to factors, such as continuous signal transformation, the fluctuation of component parameters, and the nonlinear characteristics of components, traditional fault localization methods are still facing significant challenges when dealing with large-scale complex circuit faults. Based on this, this paper proposes a fault-diagnosis method for analog circuits using the ECWGEO algorithm, an enhanced version of the GEO algorithm, to de-optimize the 1D-CNN with an attention mechanism to handle time-frequency fusion inputs. Firstly, a typical circuit-quad op-amp dual second-order filter circuit is selected to construct a fault-simulation model, and Monte Carlo analysis is used to obtain a large number of samples as the dataset of this study. Secondly, the 1D-CNN network structure is improved for the characteristics of the analog circuits themselves, and the time-frequency domain fusion input is implemented before inputting it into the network, while the attention mechanism is introduced into the network. Thirdly, instead of relying on traditional experience for network structure determination, this paper adopts a parameter-optimization algorithm for network structure optimization and improves the GEO algorithm according to the problem characteristics, which enhances the diversity of populations in the late stage of its search and accelerates the convergence speed. Finally, experiments are designed to compare the results in different dimensions, and the final proposed structure achieved a 98.93% classification accuracy, which is better than other methods.

Research on a hypothesis of performance optimization for Op-amp circuit-based neural network models

The operational amplifier (Op-amp) plays a significant role in the circuit design. This article proposes a topology of the multi-stage Op-amp circuit design and the theoretical calculations and LTSpice simulations are also involved in terms of the performance including the differential input resistance, voltage gain, output impedance, total current consumption. Since these performances are affected by some resistors and other devices in the circuit, optimization below the design specifications can be achieved by changing the corresponding parameters. This paper proposes a hypothesis that (Op-amp) can be optimized by establishing a linear regression model, and on the other hand, the paper claim that (Op-amp) can be optimized by building a neural network model, which can be achieved through Python.

Phase-locking dynamics for electronic relaxation oscillators via threshold pulse-modulation: Comparing experimental and analytical Arnold tongues

We present detailed analytical and experimental results for a system of two comparator-based relaxation oscillators that are coupled via threshold modulation. Starting with the op-amp circuit equations, we derive parameter conditions that lead to n:1 phase-locked solutions, thereby obtaining predictions for the shapes of Arnold tongues for this system. These tongues are compared to experimental data and good agreement is found. We follow up with a stability analysis of phase-locked solutions. Specifically, we use two-timescale asymptotic analysis, and we check some results obtained therein against experimentally captured dynamics.

Automatic generation of macromodels and design equations for application to Op Amp design

SummaryOperational amplifier (Op Amp) is a special class of analog integrated circuits. Multiple‐stage Op Amp design is of particular interest recently. However, analysis of this class of circuits has to be done manually and requires advanced skills. Automatic analysis of this class of circuits is studied in this paper, which takes a novel approach by circuit recognition and symbolic generation. Circuit recognition is deterministic, implemented by deterministic circuit partitioning and functional block extraction methods. Symbolic analysis of extracted circuit blocks can subsequently be performed with greatly reduced complexity while generated models and equations bear more useful information for circuit design. Symbolic results so generated can be applied in design space exploration, including tasks like finding the limitation in circuit topology, conducting initial sizing, and determining performance tradeoffs. This paper proposes the key algorithms for realizing the recognition of a few well‐known functional blocks frequently used in CMOS Op Amp circuits and further explores the possibility of using the recognized circuit cells in combination with the gm/ID method for circuit sizing. Preliminary tests show that this approach is a potential candidate for locating the performance boundaries of multiple‐stage Op Amps.

GAMMA RAY EFFECT ON OP-AMP 741 AND TIMER 555 IC

The commercial used the 555 single timer and the 741 operational amplifiers (op-amp) were investigated under the gamma-ray radiation of the Co-60 source. The maximum total doses were used 2 kGy and 4 kGy to irradiate. The abnormal behavior in the 555 single timer circuit frequency was observed, which decreased from 202 to 195 Hz at 744 Gy gamma-ray radiations. In the 741 op-amp circuit, the output signal dropped from 1.28 to 1.25 under the same radiation dose. The loss of output amplitude was calculated at about 2.3 % when the radiation dose was 4 kGy. At the same time, the gain of the 741 op-amp decreased from 9.88 to 9.84 and its slew rate drops from 4 to 0.65 V/µs. The 555 single timer has two pn junctions and these diodes cause the 555 single timer to be easily affected by gamma radiation. Consequently, the integrated circuits must be tested to determine their resistance limits in the radiation environments.

Research on portable constant pulse current source device

A set of portable constant pulse current sources with STM32 as the control core is developed, which mainly involves the SCM control module, operational amplifier circuit module, pulse output module, power module, key module, and display module. Based on the traditional constant-current source circuit design, the real-time display control system is constructed by software programming optimization, which has the characteristics of portable and strong stability. By connecting the field effect tube and operational amplifier in series to form a feedback loop, the current output accuracy is improved and the stability of the current output is ensured. The experimental results show that after the op-amp circuit is introduced into the series feedback system, the front and rear order circuit can be more stable, and ensure the reference voltage is stable at the same time, through the duty cycle of PWM wave to adjust the current output, so that the constant current source output 0~2mA adjustable low-frequency stable current. At the same time, in terms of human-computer interaction, in addition to the use of buttons to adjust the current at both ends of the load, a small OLED display screen is used to display the current, voltage, and pulse frequency in real time. The experiment shows that the instrument has high stability and load adaptability, and has high practical value.

P‐13.1: Analysis of Reduced Power Consumption in Always On Display Mode for OLED Display

This paper achieves the purpose of reducing power consumption by partitioning the driver chip in AOD mode. For non‐display areas, the Source op amp circuit of the driver chip and non‐related data processing functions are turned off to optimize power consumption. For the multi‐area display scenario in AOD mode, no matter where the black background is, this design can automatically recognize the black background and carry out power‐saving actions. At the same time, the power optimization function of 1Hz and 0.1Hz ultra‐low frequency display is analyzed.

Performance analysis of CMOS based analog circuit design with PVR variation

Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

Linear LED driver design and its implementation for visible light communication applications

This study aimed to develop a linear LED driver for VLC applications which is capable of transmitting multilevel amplitude, such as OFDM formats or pure analog audio – video signals. The proposed driver comprises a general Op-Amp circuit that emits 3–12 Watts LED power. The maximum current of an Op-Amp limits the LED power. This study characterizing the I-V curves and provide insights on how to attain the LED suitable or optimal biasing point. First, the information signal undergoes clipping due to the too high bias point. Second, the LED cannot light up because the bias point is too low. Differently from the conventional Bias-T LED drivers, we exploited the readily available components such as Op-Amp that allows to work as adder device between the data signal and the DC offset. It is also a cost-effective way that uses off-the-shelf Op-Amps. Furthermore, the driver incorporates a DC-offset remover capability for an input similar to the DC signal. The experimental results showed that the linear driver’s bandwidth (BW) is ≥ 500 kHz without affecting the LED when lighting up. Moreover, the design was evaluated with BER analysis and demonstrated with a real VLC transceiver platform. The transceiver platform comprises FPGA Zync-7000, AD7302 DAC, XADC, and an off-the-shelf Analog Front-End (AFE) receiver. The proposed linear driver was clocked at 100 kHz to perform real-time VLC transmission using QPSK modulation and maximum bit-rate measurement. We have achieved a BER of < 1.5 × 10−3 and ∼30 kbps of real-time transmission speed. Therefore, it has a huge potential in IoT-based VLC networks.

Folded Cascode Operational Amplifier Design Utilizing 0.25 µm CMOS Technology

A one-stage Folded Cascode Operational Amplifier with the self-biasing scheme for the PMOS differential input stage is designed by using LTspice simulator and the designing procedure is described. This folded op amp will have a high Common-mode input range (ICMR) and a high maximum voltage output thereby high gain. The LTspice simulation results correlate very well with the hand calculations obtained theoretical values. All the MOSFETs are kept in saturation to ensure high open loop gain. Then, a two-stage op amp circuit has been designed by assuming Zero (z)= 10 GB, and phase margin (PM= 68o). The obtained result of the output gain for this design was Avo= 91 dB, indicating that the design has a high gain.

Comparative analysis of radiation tolerant analog circuit layout in 180 nm CMOS technology for space application

This work extend the application of radiation hard by design(RHBD) techniques to circuit level and review the effectiveness of these methods based on performance of analog domain circuit in radiation environment. A 3D TCAD tool was used in simulating the different layout styles of NMOS device. The parameter like Ioff (off state leakage current), Ion(on state current), Vdsat( saturation voltage), Vth (threshold voltage), Ro (output resistance) and gm (trans-conductance) were in focus. A test chip comprising of four opamp circuits and implemented using different layout method(conventional, Half ring, Butterfly, ELT) . The test chip was fabricated in SCL’s 180 nm process and total ionization dose(TID) tolerance testing up to 300K rad was done. The findings of the work as follows: half ring and butterfly layout styles perform at par with ELT in TID tolerance test. The bandwidth and slew rate metrics of opamp employing half ring and butterfly layout were better by 25% and offer better trade-off in terms of silicon area. The quiescent current in opamp circuit implemented with RHBD technique increases by 3% but 16% increment observed for opamp circuit implemented with conventional method for radiation dose of 300K rad. The presented work can provide insights to designers for selecting the RHBD techniques for rad hard application specific integrated circuit (ASIC) design for space/defense applications.

A New Platform of Iron Oxide-Based Nanoparticles Assay Using GMR Chip-Based Sensor With Microcontroller

The low-cost, simple, and fast quantitative assay of magnetic nanoparticles (MNPs) is important for the development of magnetic-based immunoassay applications. However, the bulky sensing element and instruments of the recent iron oxide-based MNPs assays are still concerns that should be resolved. This article reports the new platform of an iron oxide-based MNPs label assay using the commercial giant magnetoresistance (GMR) chip AAL024, manufactured by Nonvolatile Electronics (NVE) Corporation, complemented with a basic differential amplifier circuit and Arduino microcontroller (AM) to acquire the digital output voltage. The as-prepared Fe3O4@Ag label possessed (15 ± 2.6) nm of average size and behaved as soft ferromagnetic with 52.1 emu/g of saturation magnetization, and 0.15 kOe of coercive field. Sensor performance for magnetic field detection, as well as Fe3O4@Ag nanoparticles label assay, was evaluated. The results show the implementation of a basic differential amplifier op-amp circuit succeed to magnify the sensor’s response to the magnetic field up to 23 times with the output voltage in the order of volt. The employment of the AM as a voltage supply of the GMR chip, an analog-to-digital converter, and a voltage gauge simplifies the data acquisition without the additional measuring instrument. Meanwhile, for the purpose of the Fe3O4@Ag nanoparticles label assay, the sensor revealed promising performance due to the high signal linearity and the rapid detection which is only 30 s with acceptable signal stabilities.

A High-Precision Sensor Based on AC Flux Cancellation for DC Bias Detection in Dual Active Bridge Converters

DC bias in a transformer is a threat to the safe and efficient operation of dual active bridge (DAB) converters. Detecting a dc component in milliamperes mixed with a large ac current is difficult. This article proposes a current sensor based on ac magnetic flux (MF) cancellation. The proposed sensor utilizes a current transformer (CT) to extract the ac component in the measured current. Then, a power op-amp copies the CT signal to an additional winding to generate an ac MF opposite to that of the main ac current. Hence, the sensor range required to measure the dc is greatly reduced for a much smaller absolute measurement error. Using only a CT and a simple op-amp circuit, the proposed solution features low complexity and power consumption. The relative error in a range of 15-A ac current is 0.038%, showing a five-fold improvement compared to off-the-shelf sensors. The proposed sensor is verified on a 1-kW DAB prototype, where the dc bias is suppressed to nearly null owing to the proposed sensor.

A TRIZ-Adopted Development of a Compact Experimental Board for the Teaching and Learning of Operational Amplifier with Multiple Circuit Configurations

Operational amplifiers (op-amps) are generally used for actualizing simple and complex electronic circuits in the subject of analogue electronics. In an effort to improve the teaching of op-amps in electronics engineering curricula, op-amp circuits in various configurations are often used for experiments in laboratory sessions so that students can acquire certain psychomotor and cognitive skills by constructing circuit connections and analyzing input–output waveforms. As a result, multiple configurations of operational amplifier circuits are often needed, requiring multiple sets of experimental boards or circuits for each experiment. This is usually not cost effective, requires more consumable electronic components, requires more maintenance and storage space in facilities, and is less user friendly for the students. Therefore, the aim of this research is to design a single, compact, and easy-to-replicate experimental board that can be converted into multiple configurations of the LM741 operational amplifier, comprising an inverting amplifier, a noninverting amplifier, a voltage follower, a summing amplifier, a differential amplifier, a differentiator, and an integrator, with minimal electronic components at a cost lower than EUR 10. The experimental board was tested with a constant input voltage of 1.0 V AC and a switching frequency of 1.0 kHz. It is capable of producing an output voltage corresponding to the individual operational amplifier configurations and can thus be used as a facilitating module for teaching and learning activities in the field of analogue electronics.

Negative Feedback Programmable Charge Amplifier for Control Piezoelectric Sensors

This paper describes the design and operation of a programmable charge amplifier for a piezoelectric sensor. An operational amplifier (op-amp) circuit operates the charge amplifier. The purpose of this paper was to design and explain a novel approach for programmable charge amplifiers. A programmable charge amplifier is created by a host digitally (Serial Peripheral Interface (SPI)) and a network of negative feedback, which is a network of resistors and capacitors (RC) connected between an output and inverter input node of an op-amp, where the feedback capacitor is 15 pF and resistors are 12.5, 25, 50, 100, and 200 k. The analog switch was used to connect serial to RC and subsequently to SPI. The suggested circuit was developed and evaluated using discrete components; also, the programmable circuit design and results were generated using Linear Technology's Integrated Circuit Emphasis (LTSPICE) simulation software. It is powered by a ±5V battery. The open loop (AOL), Noise Gain (NG), and phase margin have all been demonstrated in ac analysis. AOL and UGF are set for varied all switches (AOL 107.26 dB and UGF 8.6 MHz), however NG exhibits stability when the feedback capacitor is larger than 15 pF and the feedback resistance is fixed since the design has a Rate-Of-Closure (ROC) smaller than 20 dB. On the other side, the phase margin is also stable. When the switches (the 5-bits of SPI) are activated, the feedback capacitor is set to 15 pF, resulting in the optimum stability, output voltage, settling time, and slew rate. These have been completed in the time domain (transient analysis).

Microcontroller Controlled Inverter Application

The limited use of fossil fuels has increased the interest in renewable energy sources. Renewable energy sources are generally direct current (DC) production. The popularity of inverters converting from DC to AC is increasing due to the generation of the generated DC signal and the current grid being alternating current (AC). In this study, a computer-controlled inverter was designed with the 16F877 microcontroller chosen as the model, and frequency and amplitude controls were realized with the serial communication system of this structure. A digital-analog converter (DAC) circuit is formed by connecting the R-2R ladder type resistor to the relevant ports of the microprocessor. With the codes written to the microprocessor, the signal response was taken from the DAC circuit, and the signal response at the ports was combined with the inverter and collector operational amplifier (op-amp) circuits, and the inverter design was completed.

Performance and Security Analysis of Parameter-Obfuscated Analog Circuits

In this article, key-based obfuscation of the transistor dimensions is proposed to mask the biasing conditions of an analog circuit and, therefore, protect the circuit against intellectual property (IP) piracy. Vector- and mesh-based obfuscations are developed that provide different degrees of circuit security with tradeoffs in design complexity and area. An algorithm for the selection of an obfuscation transistor and a satisfiability modulo theory (SMT)-based algorithm that searches the design space to determine the dimensions of the obfuscation transistors are developed to reduce the computational complexity of designing and implementing the proposed parameter obfuscation techniques. The parameter obfuscation techniques, along with the developed algorithms, are implemented on an active inductor-based second-order bandpass filter (BPF) and an operational amplifier (op-amp). The results from the analysis of the obfuscated BPF and op-amp indicate that the critical circuit performances are properly locked with at least 15% variation from the target circuit parameters when setting incorrect transistor sizes. A simulation-based optimization algorithm is proposed to tune the biasing conditions and transistor body voltages, which mitigates the effects of both the parasitic impedance of the circuit and any variation due to the implementation of the obfuscation circuitry. The proposed simulation-based optimization algorithm determines the biasing conditions and body voltages of the BPF in 500 iterations and the op-amp circuit in 70 iterations, which provides a significant reduction in the design time and the number of circuit recycles. Implementing the parameter obfuscation technique with the proposed algorithms provides an efficient means to secure analog circuits while reducing the design time to implement security features.

System Design of Three Phases Six Legs DC/DC Converter for Solar Cell

this paper describes the design of full bridge DC to DC converter 3 phase six legs for solar PV. The prototype is built with 5 kHz transformers, 2 lead-acid batteries with each energy storage of 12V, 7.2Ah and 20WP solar PV. Three phase switching is provided by analog op-amp comparator circuit with variable frequency 1 kHz-20 kHz. The controller of the converter use adjustable DC power supply as voltage reference for analog op-amp comparator, works varies from 0-11VDC (0%-50% duty cycle) and controlled manually

Application Of Ba0.5Sr0.5TiO3 (Bst) Film Doped With RuO2 (0%, 2%, 4% and 6%) On A Rice-Stalk Cutting Robot Model Based On A Line Follower With Hc-05 Bluetooth Control

Ba0.5Sr0.5TiO3 (BST) film doped with RuO2 with varying concentrations (0%, 2%, 4%, and 6%) on a p-type (100) silicon substrate has been successfully grown using the Chemical Solution Deposition (CSD) method and spin coating at a rotational speed of 3000 rpm for 30 seconds. The film on the substrate was then heated at 850 oC for 15 hours. BST film+RuO2 variations were characterized for their sensitivity as a light sensor. BST film+RuO2 variations were tested with a varied light source and reflective surface colors. Thin films have a range at the visible light wavelength, so LED lights were used as the light source in the present study. The light source selected was the blue LED because it had a high contrast in differentiating between dark and light-colored surfaces. Various electronic circuits assisted sensitivity characterization with the aim to produce a sensor that is highly sensitive to light. The response of BST film+ RuO2 variations differed according to the RuO2 doping concentration. BST film doped with RuO2 6% had a very good response to changes in light, so this film was applied as the line detector sensor in the line follower-based rice-stalk cutter model with an HC-05 Bluetooth control. Before being integrated with the microcontroller, the output voltage of the BST film was strengthened using an op-amp circuit so that the microcontroller could read the output voltage of the BST film.