One-bit Processing Research Articles

Development of software for performing acoustic time reversal with multiple inputs and outputs

At Brigham Young University, acoustic time reversal experiments are conducted in solids and fluid media. The experimental setup involves synchronized generation and acquisition hardware. The synchronized hardware allows for multi-channel generation, and in some cases, multi-channel acquisition of time reversal focusing. A LabVIEW application has been compiled to increase ease of use and repeatability for the students conducting experiments. Forward and backward steps of time reversal are conducted through this simple user interface. The software is also able to control a 2D positioning system that allows for the measurement of the spatial extent of a time reversal focus. Modifications to traditional time reversal processing, such as inverse filtering and one-bit processing, may be easily implemented in the software. This presentation describes the hardware and software that help to facilitate time reversal research. Ideas from this presentation may help others develop time reversal data acquisition systems.

A Compact, High-Gain, High-Power, Ultrawideband Microwave Pulse Compressor Using Time-Reversal Techniques

Generation of high-peak-power, microwave ultrashort pulses (USPs) is desirable for ultrawideband communications and radar/remote sensing. A variety of microwave USP generators exist today, or are described in the literature, and have benefits and limitations depending on the application. A new class of pulse compressors for generating USPs using electromagnetic time-reversal (TR) techniques has been developed in the last decade and is the topic of this article. This article presents a compact TR microwave pulse-compression cavity that has ultrawide bandwidth (BW) (5-18 GHz) and employs waveguide feeds for high-peak-power output over the entire band. The system uses a time-reversal-based pulse compression scheme with one-bit processing (OBTR) to achieve high-peak power. We present results from full-wave simulations and measurements showing compression gain exceeding 21.2 dB, 22% efficiency, and measured instantaneous peak output powers reaching 39.2 kW. These are all record results for this type of pulse compressor. In addition, we present a new analysis of variation in compression gain due to impulse response recording time and BW variation, new experimental work on the effect of mode stirrer position on compression gain, and a novel RF switch-based technique for reducing time-sidelobes while using OBTR.

One-bit processing for digital control

The paper presents a new methodology and architecture for digital control. Control laws can be efficiently implemented with one-bit signals at both the input and output. ΔΣ modulation is used to shape either analogue or multi-bit digital signals into 1-bit format. The 1-bit signals can be applied directly to physical systems, i.e. pulse-density modulation. A modified canonic controller structure is developed, in which there are no multipliers. Some problems arising from sampling and quantisation are discussed. As an example, a practical 1-bit processing architecture for DC motor control is presented.

An LSI adaptive array processor

Describes an LSI adaptive array processor (AAP) for two-dimensional data processings. The AAP contains a large number of one-bit processing elements (PEs) arranged in a square array. The large degree of parallelism and control registers in each PE allow for high speed and flexible operations. High transfer capability is also obtained by a simple inter-PE connection network with hierarchical bypasses. The high applicability to various data processings is indicated by a matrix multiplication example, utilizing an algorithm similar to a systolic one. An AAP LSI composed of 8/spl times/8 PEs with powerful functions has been implemented in a 96.0 mm/SUP 2/ chip by using 2 /spl mu/m Si-gate p-well CMOS technology. A high-speed cycle time of 55 ns, low power dissipation of 1.1 W, and high packing density of 1170 transistors/mm/SUP 2/ has been achieved by a skilful manual design. Though the LSI contains as many as 111900 transistors, the design effort has only required one man-year due to cellular array regularity. This LSI is expected to realize a high-performance AAP compactly.