On-state Current Research Articles

Ultra-sensitive dengue NS1 protein detection via asymmetric source-drain, heterojunction and dual-dielectric cavities in a uniform tunnel FET biosensor

In this paper, we present a unique Asymmetric Source-Drain Heterojunction Dual-Dielectric Uniform Tunnel Field Effect Transistor (A-SD-HJ-DD-UTFET) based biosensor tailored for the early detection of dengue NS1 protein during the acute phase of infection offering early diagnosis and potentially life-saving intervention. The proposed biosensor design features simplified fabrication, a narrow drain region, and a dual material control gate, enhancing specificity and sensitivity for dengue virus detection. Using a heterojunction configuration, this device optimizes electron flow for improved detection accuracy. The roles of Tunnel Gate (TG) and Auxiliary Gate (AG) are studied in terms of band energy, electric field, electrostatic potential, and other sensitivity parameters. Sentaurus TCAD tool is utilized for analyzing the characteristics of the proposed A-SD-HJ-DD-UTFET biosensor. Simulation results indicate that the designed A-SD-HJ-DD-UTFET biosensor achieves a superior Subthreshold Swing (SS) of 15.4 mV/dec and an enhanced ION/IOFF sensitivity of about 2.25 × 10¹¹ with a maximum ON and minimum OFF state currents of 2.28 × 10–4 A/μm and 1.28 × 10–16 A/μm respectively for detecting NS1 protein of dengue. Additionally, it boasts a high switch ratio in the order of 1012. The proposed biosensor outperforms conventional devices, including the state-of-the-art Junctionless (JL)-TFET biosensors. The superior electrical characteristics of the proposed A-SD-HJ-DD-UTFET biosensor make it a promising device for early detection of the dengue NS1 protein, providing a potent solution for mitigating the spread of dengue infections.

Properties Investigation and Damage Analysis of GaN Photoconductive Semiconductor Switch Based on SiC Substrate.

The GaN photoconductive semiconductor switches (PCSSs) with low leakage current and large on-state current are suitable for several applications, including fast switching and high-power electromagnetic pulse equipment. This paper demonstrates a high-power GaN lateral PCSS device. An output peak current of 142.2 A is reached with an input voltage of 10.28 kV when the GaN lateral PCSS is intrinsically triggered. In addition, the method of retaining the AlGaN/GaN heterostructure between electrodes on PCSSs is proposed, which results in increasing the output peak current of the PCSS. The damage mechanism of the PCSS caused by a high electric field and high excitation laser energy is analyzed. The obtained results show that the high heat generated by the large current leads to the decomposition of GaN, and thus, the Ga forms a metal conductive path, resulting in the failure of the device.

Heterostructure WSe2/copper hexadecafluorophthalocyanine (F16CuPc) field-effect transistors for efficient suppression of electron transport

The use of the organic semiconductor copper hexadecafluorophthalocyanine (F16CuPc) in WSe2 based heterostructure field-effect transistors (FETs) is shown to result in a large reduction in electron current while not significantly impacting the hole current. This approach is promising for use in p-channel FETs in which electron transport is undesirable and increases leakage currents and power dissipation in the off-state. The reduction in on-state electron currents, by up to three orders of magnitude, is due to the transfer of electrons to the low-mobility states in F16CuPc due to the greater electron affinity of the organic semiconductor compared to WSe2. The off-state currents under a drain bias are reduced by more than four orders of magnitude due to the effective suppression of electron currents. This is a result of the formation of type II heterostructure between F16CuPc and WSe2. Electrons in this heterostructure FET will preferentially transfer to F16CuPc, while holes will tend to remain in the high mobility WSe2 layer. This effect is more marked in monolayer WSe2 based FETs compared to multilayer WSe2 FETs due to a larger difference in electron affinities with respect to F16CuPc. Also, the magnitude of electron current suppression was further enhanced when F16CuPc is deposited only on a part of the channel near the source of WSe2 +F16CuPc FETs.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Enhancing phase and morphology control of vanadium oxide films for resistive memory applications: A water-assisted chemical approach

This study explores the influence of precursor solution composition and solvent selection on the synthesis of vanadium oxide (VO2) thin films tailored for resistive memory applications. The vanadium pentoxide and oxalic acid molar ratio and the dispersing medium (ethanol, water, and their mixture) were varied. Water content significantly influenced the VO2 phase, morphology, and film thickness. Ethanol yielded mixed vanadium oxide phases VO2 − Tetragonal, V2O5 − Orthorhombic, and Monoclinic) and a film with minor imperfections. Conversely, the active layer prepared using an aqueous medium showed a predominant VO2 − Monoclinic phase, albeit with a non-uniform film. An ethanol–water mixture produced the most uniform morphology and a mixture of vanadium oxide phases (VO2 − Tetragonal, V2O5- Orthorhombic). All devices displayed resistive switching behavior. VO2-containing devices exhibited a more pronounced transition from an ohmic conduction state to a space-charge-limited conduction mechanism. ON-state currents remained consistent, while OFF-state currents varied notably.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Simulations of Anisotropic Monolayer GaSCl for p-Type Sub-10 nm High-Performance and Low-Power FETs.

Two-dimensional materials have been extensively studied in field-effect transistors (FETs). However, the performance of p-type FETs has lagged behind that of n-type, which limits the development of complementary logical circuits. Here, we investigate the electronic properties and transport performance of anisotropic monolayer GaSCl for p-type FETs through first-principles calculations. The anisotropic electronic properties of monolayer GaSCl result in excellent device performance. The p-type GaSCl FETs with 10 nm channel length have an on-state current of 2351 μA/μm for high-performance (HP) devices along the y direction and an on-state current of 992 μA/μm with an on/off ratio exceeding 107 for low-power (LP) applications along the x direction. In addition, the delay-time (τ) and power dissipation product of GaSCl FETs can fully meet the International Technology Roadmap for Semiconductors standards for HP and LP applications. Our work illustrates that monolayer GaSCl is a competitive p-type channel for next-generation devices.

Ballistic 2D MoS2 transistors with ultra-high on-state currents

Ballistic 2D MoS2 transistors with ultra-high on-state currents

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors.

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35mV dec-1 with a high on-state current of up to 4.9µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (μ FE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a–IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (V th), on-state current, μ FE and gate bias stress stability of a-IGZO TFTs. A significant increase in μ FE of over 8 fold, from 16 cm2 Vs−1 to 140 cm2 Vs−1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

This study aims to enhance the efficiency of the Double Gate-Junctionless-Tunnel Field Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs-based Single Material and Tri-Material (SM and TM) configurations.In order to overcome the drawbacks of present TFET architectures, such as their limited ability to drive current and their ambipolar behaviour, and to enhance the on-state current, To execute our suggested SM-TM-DG-JL-TFET configuration. The TM structure exhibits a greater on-state current (I on ) and a lower SubthersholdSwing (SS) in comparison to SM structures. This study quantifies the Unit-gain-current-cut-off-frequency (f t ) and Maximum oscillation frequency fmax by manipulating geometric parameters such as gate length(l g ), gate-oxide thickness, and Channel thickness. The TM structure exhibits a significantly greater on-state current (I on ) of 14 × 10−3 A. Compared to SM structures, while simultaneously reducing the off-state current (I off ), subthreshold swing (SS), and threshold voltage (V t ). TM structures exhibit higher values of f t and fmax in DG-JL-TFET due to their enhanced output conductance compared to SM structures. The device exhibits potential for future low-power-RF applications due to its significant values of f t and fmax .

Improved high voltage operation of amorphous In–Ga–Zn–O thin film transistor by carrier density enhancement

We report on improved high voltage operation of amorphous-In–Ga–Zn–O (a-IGZO) thin film transistors (TFTs) by increasing carrier density and distributing the high bias field over the length of the device which utilizes an off-set drain structure. By decreasing the O2 partial pressure during sputter deposition of IGZO, the channel carrier density of the high voltage a-IGZO TFT (HiVIT) was increased to ∼1018 cm−3. Which reduced channel resistance and therefore the voltage drop in the ungated offset region during the on-state. To further decrease the electric field in the offset region, we applied Ta capping and subsequent oxidation to locally increase the oxygen vacancy levels in the offset region thereby increasing local carrier density. The reduction of the drain field in the offset region from 1.90 V μm−1 to 1.46 V μm−1 at 200 V drain voltage, significantly improved the operational stability of the device by reducing high field degradation. At an extreme drain voltage of 500 V, the device showed an off-state current of ∼10−11 A and on-state current of ∼1.59 mA demonstrating that with further enhancements the HiVIT may be applicable to thin-film form, low leakage, high voltage control applications.

InP Crystal Phase Heterojunction Transistor with a Vertical Gate-All-Around Structure.

Crystal phase transitions can form a new type of heterojunction with different atomic arrangements in the same material: crystal phase heterojunction (CPHJ). The CPHJ has an inherently strong impact on band engineering without concerns over critical thicknesses with misfit dislocations and a semiconductor-metal transition. In-plane CPHJ was recently demonstrated in two-dimensional (2D) transition-metal dichalcogenide (TMD) materials and utilized for conventional planar field-effect transistor applications. However, scalability such as gate electrostatic control, miniaturization, and multigate structure have been limited because of the geometrical issue. Here, we demonstrated a transistor using the CPHJ with a vertical gate-all-around structure by forming a CPHJ in conventional III-V semiconductors. The CPHJ, composed of wurtzite InP nanowires with zincblende InP substrates, showed an atomically flat heterojunction without dislocations and indicated a Type-II band discontinuity across the junction. The CPHJ transistor had moderate to good gate electrostatic controllability with high on-state currents and transconductance. The CPHJ offer will provide a new switching mechanism and add a new junction and device design choice to the long history of transistors.

High-Performance Sub-10 nm Two-Dimensional SbSeBr Transistors through Transport Orientation.

Exploring two-dimensional (2D) materials with a small carrier effective mass and suitable band gap is crucial for the design of metal oxide semiconductor field effect transistors (MOSFETs). Here, the quantum transport properties of stable 2D SbSeBr are simulated on the basis of first-principles calculations. Monolayer SbSeBr proves to be a competitive channel material, offering a suitable band gap of 1.18 eV and a small electron effective mass (me*) of 0.22m0. The 2D SbSeBr field effect transistor (FET) with 8 nm channel length exhibits a high on-state current of 1869 μA/μm, low power consumption of 0.080 fJ/μm, and small delay time of 0.062 ps, which can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices. Moreover, despite the monolayer SbSeBr having an isotropic me*, the asymmetrical band trends enable SbSeBr FETs to display transport orientation, which emphasizes the importance of band trends and provides valuable insights for selecting channel materials.

Performance improvement of SOI Tunnel-FET using pure boron and Ge pocket layer

This article highlights the results of a source pocket-engineered heterojunction pure-boron SOI Tunnel-FET (SP-PB-TFET) for low-power applications. To achieve improved performance, a novel pure-boron silicon TFET structure is considered with Silicon–Germanium source, Germanium pocket. Based on experimental data, the on-state current of a SiGe source TFET increases with increasing Ge content in SiGe. Nevertheless, the off-state leakage current increases with the Ge content of SiGe. To mitigate the problem somewhat, a Ge-pocket could be incorporated into the source near the tunneling junction. The final results provide a high current ratio (Ion/Ioff) of 1011 and a steep subthreshold swing (SS) of 18 mV/Decade at a very low supply voltage of 0.7 V. Moreover, SP-PB-TFET is suitable for high-frequency appliances due to its high cut-off frequency. This work also addresses the impact of temperature analysis and interfacial traps on device performance. The proposed SP-PB-TFET provides excellent DC and analog performance, making it suitable for low-power, high-frequency applications.

Threshold Voltage Instability After Double Pulse Test Under Different OFF-State Drain Voltages and ON-State Drain Currents in p-GaN Gate AlGaN/GaN HEMT

This study investigated threshold voltage (VTH) instability in a Schottky p-GaN gate AlGaN/GaN high-electron-mobility transistor (HEMT) by using the double pulse test (DPT) with a 1 μs pulse width in the ON-state and OFF-state. OFF-state drain biases (VDS,OFF) of 100–400 V and ON-state drain currents of ID,ON 1–16 A were applied in the DPT to observe the post-DPT VTH shift. The ON-state currents did not strongly influence the device’s characteristics after the DPT. However, the OFF-state voltages, particularly VDS,OFF = 100 and 200 V, exerted notable effects. A TCAD simulation was conducted to investigate the mechanism underlying the VTH shift after the DPT at various VDS,OFF and ID,ON levels.

Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment

In advanced MOSFET design, a vertical-channel structure provides the advantages of a smaller footprint of the transistor cell and stronger immunity against short-channel effects by introducing higher freedom in determining the channel length. For these reasons, vertical devices are still predicted to be an upcoming solution in the most recent technology roadmap. However, due to the cell-to-cell or wafer-to-wafer processing deviation that inevitably exists, it can be quite challenging to locate the gate edges at the exact positions that maximize the device performance. In this work, a series of technology computer-aided design (TCAD) device simulations have been carried out to investigate the effects of gate underlap and overlap structures on the device performance of vertical-channel MOSFETs. The device characterizations were conducted from the aspects of both DC and HF operations for higher completeness of this work, since both are not usually optimized at the same time under the same structural and processing conditions. Under the underlap condition, slight degradation in the on-state current (I on) drivability was observed. On the other hand, a noticeable off-state current (I off) increase was witnessed under the underlap conduction. It is explicitly demonstrated that excessive gate underlap results in non-ideal effects, including degradation of the subthreshold swing (S), worsening of drain-induced barrier lowering, and lowering of the maximum transconductance (g m,Max). In the HF analyses, although f T and f max remained high under overlap and gate–drain alignment conditions, it was observed that both were likely to deteriorate under underlap conditions. As a result, a processing margin in the anisotropic etching of the gate can be obtained for the optimization of the DC and HF performance of vertical-channel MOSFETs, paving the way for a wide variety of low-power and high-speed analog and digital applications.

Integrated 2D multi-fin field-effect transistors

Vertical semiconducting fins integrated with high-κ oxide dielectrics have been at the centre of the key device architecture that has promoted advanced transistor scaling during the last decades. Single-fin channels based on two-dimensional (2D) semiconductors are expected to offer unique advantages in achieving sub-1 nm fin-width and atomically flat interfaces, resulting in superior performance and potentially high-density integration. However, multi-fin structures integrated with high-κ dielectrics are commonly required to achieve higher electrical performance and integration density. Here we report a ledge-guided epitaxy strategy for growing high-density, mono-oriented 2D Bi2O2Se fin arrays that can be used to fabricate integrated 2D multi-fin field-effect transistors. Aligned substrate steps enabled precise control of both nucleation sites and orientation of 2D fin arrays. Multi-channel 2D fin field-effect transistors based on epitaxially integrated 2D Bi2O2Se/Bi2SeO5 fin-oxide heterostructures were fabricated, exhibiting an on/off current ratio greater than 106, high on-state current, low off-state current, and high durability. 2D multi-fin channel arrays integrated with high-κ oxide dielectrics offer a strategy to improve the device performance and integration density in ultrascaled 2D electronics.

High-throughput approach to explore cold metals for electronic and thermoelectric devices

Cold metals with an energy gap around the Fermi level have been shown a great potential for reducing the power dissipation of transistors and diodes. However, only a limited number of 2D cold metals have been studied. In this work, we explored 3D cold metals through a systematic material search and found 252 types in the database. We performed first-principles calculations to investigate the conductance and work functions of 30 cold metals for material selection. Additionally, we studied the thermoelectric properties of four typical cold metals, which possess much larger Seebeck coefficients and figure-of-merits than conventional metals, by one and two orders of magnitude, respectively. Specifically, we constructed a monolayer MoS2 transistor with a cold metal contact of ZrRuSb. Our quantum transport simulations indicate that cold metal contacted MoS2 FETs exhibit a subthreshold swing smaller than 60 mV decade−1 over four decades, and on-state currents over 1 mA μm−1 are achieved at a supply voltage of 0.5 V. Our research provides a theoretical foundation and material basis for exploring 3D cold metals in developing electronic and thermoelectric devices.

Improvement of C-shaped pocket TFET with sandwiched drain for ambipolar performance and analog/RF performance

A novel structure of tunneling field effect transistor device (CSP-SD-TFET) is proposed, which adds a sandwiched drain to the C-shaped pocket TFET (CSP-TFET). This structure can increase the resistance of the drain, share the lateral electric field at the tunneling junction between the channel and the drain, reduce the lateral electric field at the tunneling junction, and suppress the generation of ambipolar current. The DC and analog/RF characteristics of CSP-SD-TFET are simulated and analyzed by Sentaurus TCAD, and the sandwiched structure parameters of the drain are optimized. The results show that the sandwiched drain structure suppresses the ambipolar current and on-state current, so the parameters of the sandwiched drain structure need to be a compromise between low ambipolar current and high on-state current. The optimized CSP-SD-TFET device has good DC characteristics, such as low average subthreshold swing SSavg (12.2mV/dec), high on/off current ratio Ion/Ioff (2.5 × 1011), high on-state current Ion (9.02 × 10−4 A/μm) and low ambipolar current Iamb (5.41 × 10−17A/μm). The RF performance of the CSP-SD-TFET, such as the cut-off frequency fT (1 × 1011 Hz) and gain-bandwidth product GBP (5.66 × 1010 Hz), are improved. It can be seen that the CSP-SD-TFET device not only has good DC characteristics but also improves analog/RF characteristics.