Increase In On-current Research Articles

Z-shaped gate tunnel FET with graphene channel: An extensive investigation of its analog and linearity performance

This work analyzes a graphene channel Z-shaped gate tunnel FET's (ZTFET) analog, and linearity performance. This research aims to introduce graphene with a two-dimensional honeycomb structure that is anticipated to be a strong challenger for the upcoming generation of semiconductor devices. The ZTFET with graphene channel provides a 3-decade increase in ON current, indicating a notable improvement in gate capacitance and transconductance compared to the conventional silicon channel. This improvement further leads to better linearity and analog/RF performance. We delved into various linearity and Radio Frequency (RF) figure-of-merits, including gmn, VIP2, VIP3, IIP3, 1‐dB compression point, GBWP, TFP, unity gain cut‐off frequency, and maximum oscillation frequency. The results of the new GC-ZTFET are compared with those of the traditional ZTFET to establish its superiority. The GC-ZTFET outshines other device structures when speaking of linearity, RF performance, and current-carrying capability.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Arrays of Bundled Semiconducting Carbon Nanotubes for High Transconductance Field Effect Transistors

Forming aligned arrays from bundled (rather than individualized) semiconducting carbon nanotubes can beneficially increase the density of nanotubes in the channel of field effect transistors (FETs). Here, we prepare aligned arrays of bundles at a density of 20 – 50 bundles μm-1 via tangential flow interfacial self-assembly and show that bundles can increase the transconductance of FETs when a strong gate is used. When encapsulated with an ion gel gate, the transconductance and saturated on-current increases as the diameter of the bundles increases. Devices tested at -0.6 V drain voltage using an ion gel gate achieve transconductance as high as 50 μS per bundle and 2000 μS μm-1 and on-state current as high as 1.7 mA μm-1. At low drain voltages the off-current also increases with bundling, but on/off ratios of ~105 are possible if the bundle size is limited to ~ 5 nm. Radio frequency devices with very strong gates may benefit from the increased device performance by using moderately bundled semiconducting carbon nanotube arrays.Figure Caption: Panel (a) has transfer curves from 4 devices each with ~42 CNTs-bundles μm-1 but with different median bundle heights. Devices with larger bundles have higher transconductance and saturated on-currents. Panel (b) shows the transconductance per bundle vs the median bundle height and shows the positive correlation between bundle size (height) and transconductance per bundle. Panel (c) is a rendering of a large bundle formed from polymer wrapped CNTs. Figure 1

A Review on SRAM Memory Design Using FinFET Technology

An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to compensate the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices faces some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, it is necessary for the memory to have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional design of the gate. FinFET has been used to improve the overall performance and has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies.

Design, simulation and analysis of high-K gate dielectric FinField effect transistor

The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i.e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, transconductance and intrinsic gain.

Effect of Back-Gate Voltage on the High-Frequency Performance of Dual-Gate MoS2 Transistors

As an atomically thin semiconductor, 2D molybdenum disulfide (MoS2) has demonstrated great potential in realizing next-generation logic circuits, radio-frequency (RF) devices and flexible electronics. Although various methods have been performed to improve the high-frequency characteristics of MoS2 RF transistors, the impact of the back-gate bias on dual-gate MoS2 RF transistors is still unexplored. In this work, we study the effect of back-gate control on the static and RF performance metrics of MoS2 high-frequency transistors. By using high-quality chemical vapor deposited bilayer MoS2 as channel material, high-performance top-gate transistors with on/off ratio of 107 and on-current up to 179 μA/μm at room temperature were realized. With the back-gate modulation, the source and drain contact resistances decrease to 1.99 kΩ∙μm at Vbg = 3 V, and the corresponding on-current increases to 278 μA/μm. Furthermore, both cut-off frequency and maximum oscillation frequency improves as the back-gate voltage increases to 3 V. In addition, a maximum intrinsic fmax of 29.7 GHz was achieved, which is as high as 2.1 times the fmax without the back-gate bias. This work provides significant insights into the influence of back-gate voltage on MoS2 RF transistors and presents the potential of dual-gate MoS2 RF transistors for future high-frequency applications.

Impact of AC Stress in Low Temperature Polycrystalline Silicon Thin Film Transistors Produced With Different Excimer Laser Annealing Energies

This letter investigates degradation during alternating current (AC) operations in low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) produced using the selective excimer laser annealing (ELA). Different degrees of degradation, on-current increase and threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) shift were observed after AC operation stress in three devices with different ELA energies. Although a higher ELA energy device has a higher on-current, this will lead to higher protrusion and a stronger electrical field in the active layer. This stronger electrical field will cause serious electron trapping in the grain boundary trap (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">trap</sub> ), leading to more serious degradation than that found in the lower ELA energy devices. Finally, COMSOL simulations and C-V measurements were executed to verify the physical mechanism.

Effects of metal content on electrical and physical properties in solution-processed IGZO thin films

The on-current of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) fabricated by solution process with low-temperature post-annealing increases monotonically with the decrease in the Ga content. This trend is different from that of IGZO fabricated by a solution process, which shows the maximum electron mobility at a Ga content of 33%. To clarify its cause, effects of Ga and In contents in solution-processed IGZO post-annealed at a low-temperature on their oxygen deficiency and band structures were investigated with spectroscopic methods such as X-ray photoelectron spectroscopy, ultraviolet photoelectron spectroscopy, photoluminescence, and ultraviolet–visible absorption. When the Ga content is low, the oxygen vacancy becomes less abundant. The increase in In content exhibits similar effects on the oxygen vacancy. We have reported that Ga is not oxidized sufficiently at low temperatures, which should cause the generation of oxygen vacancies. By this theory, the above-mentioned decrease in oxygen vacancies can be explained. Furthermore, when these films are actually used as TFT channels, the on-current increases with the decrease in Ga content. From this, in solution-processed IGZO post-annealed at a low temperature, oxygen vacancies mainly act as electron traps that decrease the on-current, rather than acting as donors. In manufacturing flexible devices, even when we decrease the process temperature low enough to suppress the damage to polymer substrates, the devices must maintain good performance. Our results suggest that an optimal metal ratio different from that of a typical vacuum process is necessary to improve the performance of IGZO TFTs fabricated by the low-temperature solution process.

Effect of physical densification on sub-gap density of states in amorphous InGaZnO thin films

In this study, we investigate the relationship between the physical densification and sub-gap density-of-states (DOS) distribution of a-IGZO films prepared under various deposition pressures. For TFTs with a-IGZO channel films, the field effect mobility increases from 10.9 to 24.8 cm2/V·s, and the on-current increases from 1.5 to 20.8 μA as the deposition pressure for the channel films decreases from 7 to 1 mTorr. The sub-gap DOS distributions obtained from the electrical characteristics indicate the changes in the density of accepter-like tail states with deposition pressure. Further, the physical densification of the channel films increases as the deposition pressure decreases. Our study demonstrates that the lower density of accepter-like tail states and the higher physical densification contribute to the improved performance of a-IGZO TFTs.

Impact of momentum mismatch on 2D van der Waals tunnel field-effect transistors

We numerically investigate electron quantum transport in 2D van der Waals tunnel field-effect-transistors in the presence of lateral momentum mismatch induced by lattice mismatch or rotational misalignment between the two-dimensional layers. We show that a small momentum mismatch induces a threshold voltage shift without altering the subthreshold swing. On the contrary, a large momentum mismatch produces significant potential variations and ON-current reduction. Short-range scattering, such as that due to phonons or system edges, enables momentum variations, thus enhancing interlayer tunneling. The coupling of electrons with acoustic phonons is shown to increase the ON current without affecting the subthreshold swing. In the case of optical phonons, the ON-current increase is accompanied by a subthreshold swing degradation due to the inelastic nature of the scattering.

Material-Device-Circuit Co-Design of 2-D Materials-Based Lateral Tunnel FETs

In this paper, the 2-D materials-based lateral TFETs are holistically assessed by co-optimizing the material parameters, device designs, and digital circuit figure-of-merits, e.g., energy consumption and delay. Effect of material parameters such as effective mass and bandgap are studied using a two-band quantum simulation approach in the ballistic regime. The selection of 2-D material parameters is discussed from the energy-delay perspective. Single-gate and double-gate 2-D TFETs are compared with the optimum material parameters. Using a simple analytical model for 2-D TFETs, the quantum simulation results for different materials and device designs are analyzed. We show that the gate-to-source fringing fields play a significant role in 2-D TFETs performance. To mitigate the effect of fringing fields on tunneling lengths, an interfacial layer (IL) is introduced between high- $\kappa $ and 2-D material, resulting a 3– $4\times $ increase in ON current. Using circuit-level metrics, we show that a tri-layer black phosphorus (BP) TFET using IL can outperform monolayer BP MOSFETs for the supply voltages below 0.5 V.

Tunable Low-Frequency Noise in Dual-Gate MoS2Transistors

We have systematically studied the effect of the back-gate voltage on the low-frequency noise properties of the MoS2 transistors from 300 to 20 K in this work. The results show that the performance of the top-gate MoS2 transistor can be effectively tuned by the back-gate voltage ${V}_{\text {bg}}$ . When ${V}_{\text {bg}}$ increases to 20 V, the maximum on-current increases up to 588 $\mu \text{A}$ / $\mu \text{m}$ for the 1- $\mu \text{m}$ channel length device, as well as five times reduction of the low-frequency noise and two times reduction in contact resistance. The Fermi-level modulation by adjusting ${V}_{\text {bg}}$ turns out to be an effective way of improving contact resistance and low-frequency noise for future high-quality MoS2 metal-oxide–semiconductor field-effect transistors.

Extremely Large Gate Modulation in Vertical Graphene/WSe2 Heterojunction Barristor Based on a Novel Transport Mechanism.

A WSe2 -based vertical graphene-transition metal dichalcogenide heterojunction barristor shows an unprecedented on-current increase with decreasing temperature and an extremely high on/off-current ratio of 5 × 10(7) at 180 K (3 × 10(4) at room temperature). These features originate from a trap-assisted tunneling process involving WSe2 defect states aligned near the graphene Dirac point.

Uniform Strain in Heterostructure Tunnel Field-Effect Transistors

Strain can strongly impact the performance of III–V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source, which allows to take full benefit of the strain-induced increase in ON-current.

Effect of stacking order on device performance of bilayer black phosphorene-field-effect transistor

We investigate the effect of stacking order of bilayer black phosphorene on the device properties of p-MOSFET and n-MOSFET. Two layers of black phosphorus are stacked in three different orders and are used as channel material in both n-MOSFET and p-MOSFET devices. The effects of different stacking orders on electron and hole effective masses and output characteristics of MOSFETs, such as ON currents, ON/OFF ratio, and transconductance are analyzed. Our results show that about 1.37 times and 1.49 times increase in ON current is possible along armchair and zigzag directions, respectively, 55.11% variation in transconductance is possible along armchair direction, by changing stacking orders (AA, AB, and AC) and about 8 times increase in ON current is achievable by changing channel orientation (armchair or zigzag) in p-MOSFET. About 14.8 mV/V drain induced barrier lowering is observed for both p-MOSFET and n-MOSFET, which signifies good immunity to short channel effects.

Gate Modulation of Threshold Voltage Instability in Multilayer InSe Field Effect Transistors

We report a modulation of threshold voltage instability of back-gated multilayer InSe FETs by gate bias stress. The performance stability of multilayer InSe FETs is affected by gate bias polar, gate bias stress time and gate bias sweep rate under ambient conditions. The on-current increases and threshold voltage shifts to negative gate bias stress direction with negative bias stress applied, which are opposite to that of positive bias stress. The intensity of gate bias stress effect is influenced by applied gate bias time and the sweep rate of gate bias stress. The behavior can be explained by the surface charge trapping model due to the adsorbing/desorbing oxygen and/or water molecules on the InSe surface. This study offers an opportunity to understand gate bias stress modulation of performance instability of back-gated multilayer InSe FETs and provides a clue for designing desirable InSe nanoelectronic and optoelectronic devices.

Tunneling field-effect transistor with a strained Si channel and a Si0.5Ge0.5 source

We report on n-channel tunneling field-effect transistors (TFET) with a tensile strained Si channel and a compressively strained Si0.5Ge0.5 source. The device shows good performance with an average subthreshold swing S of 80mV/dec over a drain current range of more than 3 orders of magnitude. We observed that the on-current increases exponentially with the back gate voltage. At a back gate voltage of 8V, the on-current was enhanced by a factor of 1.6. The back gate also improves the on/off current ratio. Low temperature measurements show a slightly temperature dependent S, characteristic for a tunneling dominated device.

Contact length scaling in graphene field-effect transistors

A study is performed on the contact length scaling in graphene field effect transistors. When the contact length (LC) is below the transfer length (LT), both transconductance and on-current increase rapidly with LC due to the strengthened carrier injection. Over the transfer length, the transconductance keeps increasing prominently before coming to a saturation. A possible explanation is that larger contact length would induce deeper doping in graphene, and the nonlinear screening of metal-induced charge could modify the potential barrier, which subsequently adjusts the contact resistance and transconductance. In principle, the electron-hole asymmetry can be tuned via altering the contact lengths.

Effect of annealing ambient and temperature on the electrical characteristics of atomic layer deposition Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and MOSFETs

In this work, we investigate the effect of forming gas annealing (FGA) on n-type and p-type In0.53Ga0.47As MOS capacitors with atomic layer deposition (ALD) Al2O3 high-κ dielectric. The as-deposited samples have a significant amount of fixed charge in the bulk of the gate dielectric and at the dielectric/semiconductor interface, which causes the flatband voltage (VFB) to have an oxide thickness dependent shift. Through FGA, we successfully (1) reduce the amount of bulk and interface fixed charge in the Al2O3, and (2) improve the Al2O3/InGaAs interface. The reduction in fixed charge is verified through an alignment of the VFB across all dielectric thicknesses. The gate stack improvement is qualitatively illustrated through a sharper capacitance-voltage (C-V) curve and quantitatively verified through a reduction of the interface trap density (DIT). The effect of the annealing temperature (300–400 °C) and ambient (N2 and forming gas (FG)) are investigated in detail through electrical characterization by C-V, I-V, DIT, fixed charge density (QF), and interface sheet charge (QIT) measurements. We find that there exists a trade-off where higher annealing temperatures result in a lower DIT, but comes at the cost of higher gate leakage. Furthermore, by comparing the effect of annealing in inert N2 versus FG, we are able to distinguish the effect of hydrogen in the FGA from the purely thermal effects of annealing. We discover that hydrogen passivation of dangling bonds and border traps is responsible for improving the interfacial properties, while the thermal budget is responsible for minimizing the fixed charge. Finally, we study the benefit of FGA on InGaAs nMOSFET device performance and demonstrate that the on-current increases by 25% after annealing at 350 °C for 30 min. A thorough understanding of the impact of FGA is crucial for threshold voltage tuning and improvement of the InGaAs MOSFET gate stack.

Illumination-Enhanced Hysteresis of Transistors Based on Carbon Nanotube Networks

The hysteresis in single-walled carbon nanotube (SWNT) transistors comprising Si backgate (SiO2 on doped Si) is normally attributed to either carrier injections from SWNTs to their surroundings or the presence of charge traps at a Si−SiO2 interface. We show that the hysteresis in SWNT transistors with a nearly trap-free Si backgate is thermally activated (activation energy Ea ∼ 129−184 meV) in a dark ambient condition, and it is attributed to hole trappings at the SiO2 surfaces proximate to SWNTs. Photon-illumination on the SWNT transistor devices with thin SiO2 dielectrics (80 nm) results in the ON-current increase due to the effective gating from the photovoltage generated at the Si−SiO2 interface. The light-induced simultaneous enhancement of ON-current and hysteresis suggests that the illumination-enhanced hysteresis is due to the photovoltage-activated hole trapping process on SiO2 surfaces.