On-chip Test System Research Articles

Recent developments in testing techniques for elastic mechanical properties of 1-D nanomaterials.

One-dimensional (1-D) nanomaterials exhibit great potentials in their applications to functional materials, nano-devices and systems owing to their excellent properties. In the past decade, considerable studies have been done, with new patents being developed, on these 1-D building blocks for for their mechanical properties, especially elastic properties, which provide a solid foundation for the design of nanoelectromechanical systems (NEMS) and predictions of reliability and longevity for their devices. This paper reviews some of the recent investigations on techniques as well as patents available for the quantitative characterization of the elastic behaviors of various 1-D nanomaterials, with particular focus on on-chip testing system. The review begins with an overview of major testing methods for 1-D nanostructures' elastic properties, including nanoindentation testing, AFM (atomic force microscopy) testing, in situ SEM (scanning electron microscopy) testing, in situ TEM (transmission electron microscopy) testing and the testing system on the basis of MEMS (micro-electro-mechanical systems) technology, followed by advantages and challenges of each testing approach. This review also focuses on the MEMS-based testing apparatus, which can be actuated and measured inside SEM and TEM with ease, allowing users to highly magnify the continuous images of the specimen while measuring load electronically and independently. The combination of on-chip technologies and the in situ electron microscopy is expected to be a potential testing technique for nanomechanics. Finally, details are presented on the key challenges and possible solutions in the implementation of the testing techniques referred above.

Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a10 kA cm−2 Nb process

Designs and test results for a single-flux-quantum (SFQ) eight-bit shiftregister circuit operating at frequencies above 100 GHz are described.The high-speed performance was realized by introducing a planarized10 kA cm−2 Nbfabrication process as an advanced process and by adopting middle-damped junctions with McCumberparameters βc of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsionbetween SFQ pulses and to adjust the timing. The circuit was designed using a cell-baseddesign method and was tested by constructing an on-chip test system with a ladder-typefour-bit high-frequency clock generator. We confirmed its correct operations up to 120GHz.

Quantitative Evaluation of the Single-Flux- Quantum Cross/Bar Switch

We demonstrated the 4 /spl times/ 4-cross/bar-40 Gbps/ch switch which is functionally compatible with a commercial semiconductor one in order to evaluate the current SFQ circuit technology quantitatively in both a operating speed and power consumption. According to our numerical simulations, the SFQ switch has one or two orders of magnitude higher throughput per a single channel than that of the semiconductor, and has much smaller exchanging times between routing paths. In an actual test based on the NEC Nb-2.5 kA/cm/sup 2/ junction technology, correct operation using an on-chip test system made up of 4700 Josephson junctions was confirmed up to 37 Gbps/ch which is about 14 times faster than the semiconductor of 2.7 Gbps/ch speed. We also confirmed that SFQ circuits consumed 1/800 power compared with those of semiconductor. The reason why data rates obtained experimentally did not reach the designed speed of 40 Gbps/ch is due to both the timing error and the influence of magnetic fields caused by large bias currents exceeding 500 mA. These results of quantitative evaluation show that the SFQ technology has much greater potentials than the semiconductor one in both the operating speed and the power consumption, which means it is very effective to apply the SFQ technology to digital applications.

High-speed testing of tandem-Banyan network switch component

We present the high-speed test results of a tandem-Banyan network switch (TBNS) component based on superconductor single-flux-quantum technology. The tested circuit is called a transmission checker (TMC) and is one component of the TBNS. The circuit was designed by using the CONNECT SFQ cell library developed for NEC standard fabrication technology. To perform the high-speed test, an on-chip test system composed of shift resisters and a high-speed clock generator were integrated together with the TMC circuit. The total number of Josephson junctions, including the on-chip test system, was 1545. We observed correct output waveforms at up to 40 GHz. The bias margin of the TMC circuit was ±6.1% up to 27 GHz and ±1.7% at 40 GHz.

High-Speed Operation of a Single-Flux-Quantum (SFQ) Cross/Bar Switch up to 35 GHz

Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.

Development of In-Situ Surface Observation System with an Atomic Resolution under Tensile Stress by Atomic Force Microscope.

A new in-situ surface observation system under tensile stress with an atomic resolution has been developed for the purpose of the explanation of the deformation of the surface and the crack growth mechanism for thin films in the micro- and nano-mechanical systems. The mechanical properties such as Young's modulus can be determined at the same time. This observation system consists of the on-chip tensile testing system and a commercialized atomic force microscope (AFM). The on-chip testing system is characterized by a static loading mechanism with a flat spring and a test chip of single-crystal silicon of 15×15×0.5 mm. Particular attention has been paid to the suppression of the vibration which effects on images of the surface with an atomic resolution. Atomic images of the surface of mica can be observed under various tensile strains till the occurrence of the fracture. The growth of the cracks and Young's modulus for TiN thin film deposited on silicon (100) specimen can be also clarified.

Demonstration of the SFQ pipelined circuit at 14 GHz

We have tested a pipelined SFQ circuit at high clock frequencies using the on-chip test system. The circuit under test (CUT) is a half adder (HA), which has the structure of a two-stage pipeline. To simplify the on-chip test system, a two bit-shift register (SR) is added to the HA. This SR has a “Data-Out” terminal and a “Tap-Out” terminal, which are connected to the two “Input” terminals of the HA. This structure reduces the number of the input terminals of the CUT to one terminal and is regarded as one of the basic component of the digital filter. We have confirmed that the CUT operates correctly with wide bias margins up to 14 GHz.

Development of In-Situ Surface Observation System with an Atomic Resolution under Tensile Stress by Atomic Force Microscope

ABSTRACTA new in-situ surface observation system under tensile stress with an atomic resolution has been developed for the purpose of the explanation of the deformation of the surface and the crack growth mechanism for thin films in the micro- and nano-mechanical systems. The mechanical properties such as Young's modulus can be determined at the same time. This observation system consists of the on-chip tensile testing system and a commercialized atomic force microscope (AFM). The on-chip testing system is characterized by a static loading mechanism with a flat spring and a test chip of single-crystal silicon of 15×15×0.5 mm. Particular attention has been paid to the suppression of the vibration which effects on images of the surface with an atomic resolution. Atomic images of the surface of mica can be observed under various tensile strains till the occurrence of the fracture. The growth of the cracks and Young's modulus for TiN thin film deposited on silicon (100) specimen can be also clarified.

On-chip test of the shift register for high-end network switch based on cell-based design

We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

High-speed operation of RSFQ circuits up to 30 GHz

We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlOx/Nb junction technology with Jc = 2.5 kA cm-2. We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing Ic. As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.

Advanced on-chip test technology for RSFQ circuits

We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.