On-chip Test Pattern Generator Research Articles

A Scalable Test Structure for Multicore Chip

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper reports an efficient synthesis scheme for pseudorandom pattern generators (PRPGs) of arbitrary length. The <formula formulatype="inline"> <tex Notation="TeX">$n$</tex></formula>-bit PRPG, synthesized in linear time <formula formulatype="inline"><tex Notation="TeX">$(O(n))$</tex></formula>, generates quality pseudorandom patterns leading to a highly efficient test logic for the very-large-scale integration (VLSI) circuit. The cascadable structure of proposed <formula formulatype="inline"><tex Notation="TeX">$n$</tex></formula>-cell PRPG is utilized to construct the <formula formulatype="inline"><tex Notation="TeX">$(n+1)$</tex> </formula>-cell PRPG, in two time steps, without sacrificing the pseudorandomness quality. This eases the design of on-chip test pattern generators for the system-on-a-chip implementing multiple cores. It avoids the requirement of disparate test hardware for different cores and thereby ensures drastic reduction in the cost of test logic. The effective characterization of nonlinear cellular automata (CA) provides the foundation of such a design. Extensive experimentation confirms the better efficiency of the proposed test structure compared to that of the conventional designs, developed around maximal length CA/linear feedback shift register of <formula formulatype="inline"><tex Notation="TeX">$O(n^{3})$</tex> </formula> complexity. </para>

A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT

Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

High performance dense ring generators

This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.

Algorithm for the generation of SIC pairs and its implementation in a BIST environment

Built-in self test (BIST) techniques provide for on-chip test pattern generation and response verification operations, and therefore constitute an efficient alternative to external testing for the detection of faults appearing in VLSI circuits. Failure mechanisms that commonly appear in high-speed CMOS VLSI circuits cannot be modelled adequately as stuck-at faults. The detection of these faults requires the application of pairs of patterns to the inputs of the circuit under test. Single input change (SIC) pairs are pairs of patterns where the first pattern of each pair differs from the second pattern in exactly one bit. SIC pairs have been proved to be extremely useful for the detection of stuck-open and delay faults. In this paper a novel algorithm for the generation of SIC pairs is presented, termed decoder-based SIC pair generation (DSG) algorithm. An implementation of the DSG algorithm in a BIST environment is also presented. The number of memory elements utilised is the lowest reported in the literature.

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the proposed on-chip Deterministic Test Pattern Generator (DTPG), can achieve not only complete Fault Coverage (FC) but also minimum test sequence by applying a selective number of pseudorandom patterns. Furthermore, the hybrid pattern BIST is designed under the resource constraint of target FPGA core so that it can be implemented on any size of FPGA core and take full advantage of the target FPGA resource to reduce test cost. Moreover, the reconfigurable core-based approach has minimum hardware overhead since the FPGA core can be reconfigured as normal mission logic after testing such that it eliminates the hardware overhead of BIST logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach.

Test generation for embedded circuits under the transparent-scan approach

A new test generation procedure is introduced for scan circuits under an approach called transparent-scan. The new test generation procedure targets a circuit-under-test that is embedded in a larger design (it is also applicable to an interconnection of embedded circuits). Transferring deterministic test data to the primary inputs of an embedded circuit from an external source can be expensive. This problem is alleviated as follows. The test generation procedure starts from a given input sequence Ψ that specifies the values of the original primary inputs of the circuit (the primary inputs before scan was added). In this implementation, Ψ is a random input sequence that can be generated by an on-chip test-pattern generator (e.g. a linear-feedback shift register) driving the original primary inputs of the circuit. The test generation procedure transforms Ψ into a test sequence T for the scan circuit under the transparent-scan approach by adding to Ψ the values of the scan select and scan chain inputs. These inputs are easily controllable from the primary inputs of the design.

Generation of Test Patterns Without Prohibited Pattern Set

This work reports the design of a fool proof on-chip test pattern generator (TPG) for very large scale integration circuits. The TPG is designed to generate pseudorandom test patterns without a given prohibited pattern set (PPS). It ensures desired pseudorandom quality of the generated test patterns and maintains fault coverage close to the figures achieved with a conventional maximal length linear feedback shift register/cellular automaton (CA)-based TPG. The theory of vector subspace generated by a CA (Chaudhuri, 1997) has provided the foundation of this design. The proposed TPG does not incur any additional cost for the avoidance of PPS.

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].

Von Neumann hybrid cellular automata for generating deterministic test sequences

We propose an on-chip test pattern generator that uses an one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) using a finite number of CA cells. Given a pair of columns (C u , C v ) of the test matrix, the proposed method uses alternative “link procedures” P j that compute the number of extra CA cells to enable the generation of (C u , C v ) by the CA. A systematic approach uses the link procedures to minimize the total number of needed CA cells. The performance of the scheme depends on an appropriate choice of link procedures P j .

Clock-driven on-chip testing for superconductor logic circuits

We have developed and demonstrated a clock-driven on-chip testing (CDOT) method for high-speed testing of superconductor logic circuits. This testing method uses an on-chip signal-pattern generator (SPG) driven by a clock signal. The SPG is based on a feedback shift register, in which a complement output of the last-stage D-flip-flop is fed back to the first-stage D-flip-flop. Thus, SPG generates a periodic signal-pattern when a clock signal is applied to it. The advantages of this testing method are that: (a) no external control signal is needed; (b) a simple SPG that consists of only D-flip-flops is used; (c) it is easy to extend to multi-bit testing. This greatly simplifies high-speed testing and design of test circuits. We have applied this method to the high-speed testing of the ring interface (RIF) circuit, which is an elemental circuit in our superconducting ring-network system. We have designed a test circuit, consisting of the RIF circuit and a 12-bit on-chip test-pattern generator, with resistor-coupled Josephson logic (RCJL). The test circuit includes about 1,400 Josephson-junctions. It has been fabricated using Nb/AlO/sub x//Nb Josephson-junction technology. As the result of the high-speed testing, full operation of the RIF circuit at 1-GHz clock frequency and proper operation of a sending part of the RIF circuit at 2-GHz clock frequency have been successfully verified.

Pseudo-exhaustive built-in TPG for sequential circuits

We address the issue of pseudo-exhaustive test pattern generation (TPG) for the built-in self-test (BIST) of sequential circuits. Let d be the sequential depth, and w be the input dependency limit. We use an LFSR/SR Test Pattern Generator and a small additional hardware overhead to automatically generate d/spl middot/2/sup w/ test patterns to test the circuit pseudo exhaustively or, alternatively, pseudo-randomly with less hardware overhead and extremely high fault coverage. Our scheme uses novel retiming algorithms and transforms the circuit to an equivalent (for test purposes) one by scanning a subset of flip-flops for breaking its cyclic structure, bounding the sequential depth, forcing the input dependency limit, balancing the circuit, and maintaining the clock period. We present the first polynomial time algorithm to bound the sequential depth of a circuit by retiming with minimum number of flip-flops and subject to a clock period bound. We also give a retiming-based polynomial time algorithm to balance a circuit by inserting a minimum number of bypass delay cells. Experimental results on the ISCAS'89 benchmarks indicate that our method outperforms a previously proposed approach, which not only does not provide for on-chip test pattern generation but also requires O(q/spl middot/f/spl middot/2/sup w/) test patterns, where q is the total number of primary or pseudo-primary outputs in the circuit and f is the total number of flip-flops.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cellular automata-based built-in self-test structures for VLSI systems

Some of the fundamental algebraic properties of hybrid additive, null-bounded, cellular automata (HACA) are presented. Simple HACA have been obtained by spatially alternating additive rules 90 and 150 (in Wolfram&apos;s notation). The use of such HACA for on-chip pseudorandom test pattern generation is also described. The great advantage of HACA over linear feedback shift registers (LFSR), as their size increases, is the fact that HACA display locality and topological regularity, important attributes for VLSI implementation.

An efficient on-chip deterministic test pattern generation scheme

Cellular automata (CA) generating cyclic groups are proposed for on-chip deterministic test pattern generation. In order to arrive at an optimum solution, algorithms are provided for generation of relevant cycles covering the desired test set. Further refinement steps have been proposed to arrive at a cost-effective solution. The detailed analysis of the AT 2 costs in each step of the execution has been carried out. Based on this analysis the method of selection of the most appropriate group rule has been reported.