On-chip Power Delivery Networks Research Articles

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis

A Stabilizing Centralized Controller for On-Chip Power Delivery Networks

A major challenge currently facing integrated systems, such as microprocessors and systems-on-chip is power delivery. With increasing system size and complexity, multiple voltage regulators are often needed for a single power domain. This connection raises non-trivial stability issues that often render the system useless. It is therefore of great practical interest to tackle the stability of such systems. This brief proposes the design of a centralized controller with the aim of rendering such power delivery networks (PDNs) stable without compromising their performance. Theoretical results are confirmed with extensive transistor-level simulations and demonstrate that the controller is capable of stabilizing PDNs with much greater area efficiency than conventional techniques.

A Multicore Chip Load Model for PDN Analysis Considering Voltage–Current-Timing Interdependency and Operation Mode Transitions

Power consumption and current fluctuation are continuously increasing in modern multicore systems. Such current flow may cause severe supply noise via off-chip and on-chip power delivery networks (PDN). Unexpected noise impacts the chip delay performance or even causes malfunction. In traditional practice, PDN designers assume a simple current source-based chip load, but it is often oversimplified, where the load current is modeled only for one or a few operation modes, and it is constant irrelevant to supply noise. In this paper, we propose a new chip load model that enables even off-chip PDN designers to assess the noise impact on circuit performance and use realistic current profile under supply voltage noise. We also integrate a control signal interface so that the model can switch the processor operation modes for finding unexpected noise behavior in design time and pursuing robust PDN design. Experimental results show that the proposed model mostly described by Verilog-A reproduces the current profile, current peak, and timing data well even while it achieves over $300\times $ run-time reduction compared to a transistor-level model. We also experimentally demonstrate that a land-side capacitor is helpful to improve processor timing performance in our test case.

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors

The increasing power density and, therefore, current consumption of high-performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate the high-frequency noise that results due to resonance between the package inductance and the on-chip capacitance. A novel circuit technique is proposed to suppress high-frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor (decap) for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the on-chip power distribution network are suppressed by up to 60% as compared with MIM or deep trench decaps of the same capacitance. In addition, there is no added latency to react to power supply noise, and there is no degradation to circuit performance as compared with existing techniques in commercial products and literature.

Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)

Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to determine the proper operation of the integrated circuits at the design phase, but is made very difficult by the sheer size of modern power grids, reaching quite a few million nodes in nanometer-scale integrated circuits. This paper presents two efficient and highly parallel preconditioning mechanisms for the analysis of large-scale power grids of near-2-D structure (with small via resistances) or 3-D structure (with large via resistances) by iterative solution methods. The proposed preconditioners approximate the matrices of practical power grids well enough to ensure fast convergence of the iterative method, while their application within the core of the method is based on a fast transform solver which makes use of a series of independent fast Fourier transforms. Apart from the near-optimal operation complexity, the main characteristics of a fast transform solver are the large degree of multilevel parallelism and low memory requirements, which enable harnessing the computational resources of massively parallel architectures like graphics processing units (GPUs). Experimental evaluation of the proposed methodology on a set of large-scale industrial benchmarks demonstrates nearly two orders of magnitude speedup and reduction in memory footprint over parallel implementations of state-of-the-art direct and iterative methods, when GPUs are utilized.

Modeling and Analysis of PDN Impedance and Switching Noise in TSV-Based 3-D Integration

This paper reports on modeling and analysis of power delivery network (PDN) impedance and switching noise in through silicon via (TSV)-based 3-D integration. PDN is simulated in SPICE with the combination of lumped-element models and distributed-element models, where the elements are extracted from full-wave electromagnetic modeling. PDN impedance explicitly distinguishes the contributions from off-chip PDN and on-chip PDN, and reveals the TSV-induced resonant effect associated with the 3-D chip stack. The simultaneously switching noises in PDN are simulated and analyzed in different frequency regions, in which 3-D integration has distinct impacts on the PDN impedance.

Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.

De-Embedding 기술을 이용한 IC 내부의 전원분배망 추출에 관한 연구

IC 내부의 전원분배망(PDN: Power Delivery Network) 회로를 분석하기 위해서는 IC의 디자인 정보가 담긴 파일이 필요하지만, 상용 IC(Commercial IC)의 경우 보안상의 이유로 디자인 정보를 제공하지 않고 있다. 하지만 온-칩 전원분배망(On-chip PDN) 특성이 포함된 경우에는 PCB와 패키지의 특성만으로는 정확한 해석이 어려우므로 본 연구에서는 IC 내부의 정보가 제공하지 않는 전원분배망(PDN) 회로의 추출에 관하여 연구를 하였다. IC 내부의 전원분배망(PDN)의 주파수에 대한 특성을 추출하기 위하여, IEC62014-3에서 제안하고 있는 추출용 보드를 제작하였고, 추출용 보드를 구성하고 있는 SMA 커넥터, 패드, 전송 선로, 그리고 QFN 패키지의 주파수에 대한 특성들을 분석하였다. 추출된 결과들은 디임베딩(de-embedding) 기술에 적용하여 IC 내부의 전원분배망(PDN) 회로를 S-parameter 기반으로 모델을 추출하였고, 평가용 보드의 전원분배망 결합회로(PDN Co-simulation)모델에 적용하여 측정과 비교한 결과, ~4 GHz까지 잘 일치하였다. GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

Locality-Driven Parallel Static Analysis for Power Delivery Networks

Large VLSI on-chip Power Delivery Networks (PDNs) are challenging to analyze due to the sheer network complexity. In this article, a novel parallel partitioning-based PDN analysis approach is presented. We use the boundary circuit responses of each partition to divide the full grid simulation problem into a set of independent subgrid simulation problems. Instead of solving exact boundary circuit responses, a more efficient scheme is proposed to provide near-exact approximation to the boundary circuit responses by exploiting the spatial locality of the flip-chip-type power grids. This scheme is also used in a block-based iterative error reduction process to achieve fast convergence. Detailed computational cost analysis and performance modeling is carried out to determine the optimal (or near-optimal) number of partitions for parallel implementation. Through the analysis of several large power grids, the proposed approach is shown to have excellent parallel efficiency, fast convergence, and favorable scalability. Our approach can solve a 16-million-node power grid in 18 seconds on an IBM p5-575 processing node with 16 Power5+ processors, which is 18.8X faster than a state-of-the-art direct solver.

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μ V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation

As the technology scales into 90 nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering log-normal leakage current variations with spatial correlation. The new analysis is based on the Hermite polynomial chaos (PC) representation of random processes. Different from the existing Hermite PC based method for power grid analysis (Ghanta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">al</i> ., 2005), which models all the random variations as Gaussian processes without considering spatial correlation, the new method consider both wire variations and subthreshold leakage current variations, which are modeled as log-normal distribution random variables, on the power grid voltage variations. To consider the spatial correlation, we apply orthogonal decomposition to map the correlated random variables into independent variables. Our experiment results show that the new method is more accurate than the Gaussian-only Hermite PC method using the Taylor expansion method for analyzing leakage current variations. It is two orders of magnitude faster than the Monte Carlo method with small variance errors. We also show that the spatial correlation may lead to large errors if not being considered in the statistical analysis.