On-chip Memory Research Articles

High-throughput software LDPC decoder on GPU

The new or future communication systems require much higher flexibility and scalability to support diverse scenarios. In this paper, a high-throughput low-density parity-check (LDPC) decoder on graphics processing unit is presented to meet the flexible and scalable requirements. A memory-reduced forward/backward approach for the check node update is proposed. Moreover, elaborate on-chip memory allocations are conducted to improve memory bandwidth. The proposed (26112, 8448) 5G LDPC decoder on RTX4090 achieves 27.6 Gbps decoding throughput with five layered iterations, while the latency is less than 1 ms. Compared with related works, the throughput speedups obtained by the presented LDPC decoder are from 1.18×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$1.18\ imes$$\\end{document} to 12.4×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$12.4\ imes$$\\end{document}.

A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of 128×128, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%.

Thermally tuned on-chip optical memory

Phase-change materials, known as Chalcogenide alloys, are a promising alternative to traditional random-access memory. They possess characteristics that are particularly beneficial for non-volatile storage applications. The features of the Phase change material Ge-Sb-Te alloy (GST) used for substrate-integrated optical memory include scaling, quick switching times, minimal switching energy, and exceptional thermal stability. The material has two tuneable states, amorphous and crystalline, with the amorphous layer for loading data optically. In contrast, the crystalline state holds the data longer without significant loss. The study designed a classic thermally tuned optical memory on a silicon substrate. It demonstrated a dependency of lattice structure on external voltage and revealed a large storage capacity for information in the form of an optical signal. The heat transport simulation utilized the Heat Transport (HEAT) solver of the Finite Element Eigenmode (FEEM) solver. At the same time, the optical response analysis involved the Finite Difference Time Domain (FDTD) solver of Lumerical. The proposed structure exhibits a memory-switching phenomenon when a temperature shift of about 60 °C from room temperature is induced by a change in the external voltage of 147 mV. These findings have substantial implications for non-volatile storage memory development, providing a potential solution for high-capacity, low-energy data storage.

(Invited) Novel Neuromorphic Computing Paradigms Enabled By Emerging Memory Devices

Implementation of Artificial Intelligence and Machine Learning algorithms on conventional Von Neumann computing architectures are crippled by the memory-wall bottleneck. To overcome these issues, novel computing architectures with high-bandwidth memories, in-memory computing, and near-memory computing capabilities are being developed. Almost all of these architectures will benefit from high-density on-chip non-volatile memories, offered by the emerging non-volatile memory devices. Additionally, emerging memory devices offer rich device physics that can be leveraged for the implementation of novel computing paradigms. This paper will talk about three such emerging memory technologies: Vertical-Thin Film Transistors-Resistive Random Access Memory (V-TFT-RRAMs), Gated-RRAMs, and Ferroelectric Field Effect transistors (FeFETs). A comparative studies of various conventional neuromorphic computing approaches that can be implemented using these devices will be discussed. Finally, materials and device requirements and pending challenges will be discussed by successful realization of the proposed computing approaches. Implementation of Artificial Intelligence and Machine Learning algorithms on conventional Von-Neumann computing architectures are crippled by the memory-wall bottleneck. To overcome these issues, novel computing architectures with high-bandwidth memories, in-memory computing, and near-memory computing capabilities are getting developed. Almost all of these architectures will benefit from high-density on-chip non-volatile memories, offered by the emerging non-volatile memory devices. Additionally, emerging memory devices offer a rich set of device physics that can be leveraged for the implementation of novel computing paradigms. This paper will talk about three such emerging memory technologies: Vertical-Thin Film Transistors-Resistive Random Access Memory (V-TFT-RRAMs), Gated-RRAMs, and Ferroelectric Field Effect Transistors (FeFETs). A comparative studies of various unconventional and brain-inspired neuromorphic computing approaches that can be implemented using these devices will be discussed. Finally, materials and device requirements and pending challenges will be discussed for these device technologies.

(Invited) Oxide Semiconductor Gain Cell Memory

The energy and delay consumed by the off-chip memory (DRAM) and memory-to-logic chip data movement becomes the bottleneck (known as the memory wall) for the computing systems nowadays, especially for abundant-data computing and neural network accelerators. Larger on-chip memory capacity with high bandwidth can be a solution, yet it is difficult to achieve using SRAM and DRAM. Oxide semiconductor FET (OSFET)-based gain cell memory on the logic platform provides higher density than SRAM due to 3D stacking and is an attractive complement to off-chip DRAM. OSFET with extremely low leakage is used as the write transistor for long retention time, while the read transistor can either adopt OSFET for multiple-layer stacking (OS-OS gain cell) or Si FET for higher read speed (Hybrid gain cell). Designing OSFET gain cell is more than simply choosing materials/device designs that have the lowest off-state leakage current for the longest retention time. Atomic Layer Deposition (ALD) Indium Tin Oxide (ITO) FET is chosen to balance retention time with memory bandwidth. With material, process, and device co-design, the ITO films deposited by ALD with TMIn precursor, 9:1 In:Sn cycle ratio, and 2nm thickness exhibited optimized characteristics for OSFET-based gain cell. The experimentally optimized device exhibits low off-current 2×10-18 A/µm, high on-current 26.8 µA/µm, low SS 70 mV/dec, and high mobility 27 cm2/Vs. It also shows good stability with small VTH shift < 0.2 V under 125 °C, low PBS shift < 0.35 V and low NBS shift < 0.1 V under 1000s bias stress. Oxide semiconductor transistors is an accumulation mode transistor that requires a gate electric field to turn off the transistor. The transistor design calls for nanometer-thin oxide semiconductor channels. Significant device design tradeoffs exists between high on-current, low off-current, short gate length scalability, and the setting of proper threshold voltages. This talk will give an overview of the above experimental achievements today and the device design considerations for future gain cell memories.

STORMM: Structure and topology replica molecular mechanics for chemical simulations.

The Structure and TOpology Replica Molecular Mechanics (STORMM) code is a next-generation molecular simulation engine and associated libraries optimized for performance on fast, vectorized central processor units and graphics processing units (GPUs) with independent memory and tens of thousands of threads. STORMM is built to run thousands of independent molecular mechanical calculations on a single GPU with novel implementations that tune numerical precision, mathematical operations, and scarce on-chip memory resources to optimize throughput. The libraries are built around accessible classes with detailed documentation, supporting fine-grained parallelism and algorithm development as well as copying or swapping groups of systems on and off of the GPU. A primary intention of the STORMM libraries is to provide developers of atomic simulation methods with access to a high-performance molecular mechanics engine with extensive facilities to prototype and develop bespoke tools aimed toward drug discovery applications. In its present state, STORMM delivers molecular dynamics simulations of small molecules and small proteins in implicit solvent with tens to hundreds of times the throughput of conventional codes. The engineering paradigm transforms two of the most memory bandwidth-intensive aspects of condensed-phase dynamics, particle-mesh mapping, and valence interactions, into compute-bound problems for several times the scalability of existing programs. Numerical methods for compressing and streamlining the information present in stored coordinates and lookup tables are also presented, delivering improved accuracy over methods implemented in other molecular dynamics engines. The open-source code is released under the MIT license.

Design of RISC-V out-of-order processor based on segmented exclusive or Gshare branch prediction

To address the balanced requirements of performance, power consumption, and area in embedded systems, this paper introduces a 32-bit out-of-order processor based on the RISC-V instruction set, and the processor supports interrupt handling. This processor is designed to support the RV32IMC instruction subset and utilizes a four-stage pipeline structure featuring sequential instruction fetching, out-of-order execution, and out-of-order write-back. The main contributions are as follows:1) The segmented exclusive or G-share branch prediction scheme for embedded processors is proposed, which provides high branch prediction accuracy when the capacity of pattern history table (PHT) is small. 2) The work undertaken by hardware and software during interrupt response is reasonably divided, which allows for fast interrupt response with minimal resource consumption. Furthermore, the interrupt response time in vectored mode is reduced by simultaneously stacking the control and status registers (CSRs) and obtaining the interrupt service routine (ISR) entry address. Executing branch prediction-related programs within an identical environment, the processor detailed in this paper demonstrates an average prediction accuracy improvement of 1.2 % over G-share and 0.6 % over bi-mode branch prediction when employing the segmented exclusive or G-share branch prediction scheme. Building on this foundation, the on-chip debugging system and memory management unit have been implemented. The processor reaches 1.389 Dhrystone/MHz and 2.802 Coremark/MHz.

FPGA-based tiling scheme and on-chip memory scheduling scheme for multi-branch semantic segmentation neural network accelerator

Abstract According to the characteristics of a multi-branch semantic segmentation neural network with a large amount of intermediate data during the inference process, we reduce the requirement of off-chip memory access and the redundant calculation due to tiling through better blocking scheme, better on-chip memory partitioning scheme, and on-chip memory scheduling scheme, improving the energy efficiency to 77.4 GOPS/W.

High Performance CNN Accelerators based on Hardware and Algorithm Co-Optimization

The efficacy of convolutional neural networks (CNNs) has led to their extensive application in picture recognition and categorization. Nevertheless, embedded systems face challenges when it comes to storing the massive volumes of weight data required by CNNs in their on-chip memory. Pruning a convolutional neural network (CNN) model can reduce its size with no impact on accuracy; however, when used with a parallel architecture, the resulting model will be slower to execute. A CNN compression method that is hardware-centric is introduced in this paper. A model of a deep neural network (DNN) will include "pruning layers (P-layers)" and "no-pruning layers (NP-layers)" attached to it. For effective and parallel processing, an NP-layer employs a regular distribution for its weights. Pruning causes a P-layer to have an irregular form, yet the high compression ratio it yields makes the shape undesirable. Using uniform and gradual quantization methods, we can achieve a processing efficiency/compression ratio trade-off with a small loss of precision. Integrating multiple parallel finite impulse response (FIR) filters into an NP-layer distributed convolutional architecture, we further improve the regular model. The P-layer irregular sparse model is suggested to use an ADF-based processing element. The suggested compression strategy and hardware architecture can be utilised by a hardware/algorithm co-optimization (HACO) method to run an NP→P hybrid compressed CNN model on FPGAs. The VGG-16 network achieves a compression ratio of 27.5× with a top-5 accuracy loss of 0.44% by using a hardware accelerator on a single FPGA chip without off-chip memory. A result of 83.0 FPS, or 1.8 times quicker, was achieved when the compressed VGG-16 model was implemented on a Xilinx VCU118 evaluation board for image applications. Index Terms - CNN, Accelerators, Co-Optimization.

Hardware Efficient Integrated In-loop Filter for HEVC Encoder

The deblocking filter (DF) and the sample adaptive offset (SAO) filter, which aids in enhancing the subjective quality of the image, make up the in-loop filter of the high-efficiency video coding (HEVC) encoder and decoder. The in-loop filter significantly increases the computational load on the HEVC encoder. It is challenging to design an in-loop filter on hardware that can handle intensive computations while using the least amount of on-chip memory, taking external memory traffic and dependencies simultaneously delivering high throughput to support Ultra HD video applications. The proposed design employs the following strategies to address these issues. This work proposes an address generation technique for pipelined horizontal and vertical filtering in DF, that avoids a transpose buffer which otherwise is required. This enables easy pipelining and parallelization thus improving throughput while reducing the on-chip memory utilization. A simplified SAO filter with parallel-pipelined processing is included in the design. These features enable the design to support ultra-HD 7680 × 4320 @ 40 fps video applications. The proposed hardware architecture has a total gate count of 7.73 K LUTs and 2.8 K slice registers, and it is implemented on a 28 nm field programmable gate array (FPGA) platform.

A Fast GPU Schedule For À-Trous Wavelet-Based Denoisers

Given limitations of contemporary graphics hardware, real-time ray-traced global illumination is only estimated using a few samples per pixel. This consequently causes stochastic noise in the resulting frame sequences which requires wide filter support during denoising for temporally stable estimates. The edge avoiding à-trous wavelet transform amortizes runtime cost by hierarchical filtering using a constant number of increasingly dilated taps in each iteration. While the number of taps stays constant, the runtime of each iteration increases in these usually memory-throughput bound shaders with increasing dilation, because the increasing non-locality negatively impacts cache hit rates. We present a scheduling approach that optimizes usage of the memory subsystem by permutating global invocation indices in such a way that each wavelet filter iteration is applied through undilated taps. In contrast to prior approaches, our method has identical performance characteristics in each iteration, effectively decreasing maintenance cost and improving performance predictability. Furthermore, we are able to leverage on-chip memory and hardware texture interpolation. Our permutation strategy is trivial to integrate into existing wavelet filters as a permutation before and after each level of the wavelet filter. We achieve speedups between 1.3 and 3.8 for usual wavelet configurations in Monte Carlo denoising and computational photography.

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers

Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies such as SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84× less space and 2.62× less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilized Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36× and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41× and 11%, respectively, compared to baseline MLC LLCs.

Surpassing millisecond coherence in on chip superconducting quantum memories by optimizing materials and circuit design.

The performance of superconducting quantum circuits for quantum computing has advanced tremendously in recent decades; however, a comprehensive understanding of relaxation mechanisms does not yet exist. In this work, we utilize a multimode approach to characterizing energy losses in superconducting quantum circuits, with the goals of predicting device performance and improving coherence through materials, process, and circuit design optimization. Using this approach, we measure significant reductions in surface and bulk dielectric losses by employing a tantalum-based materials platform and annealed sapphire substrates. With this knowledge we predict the relaxation times of aluminum- and tantalum-based transmon qubits, and find that they are consistent with experimental results. We additionally optimize device geometry to maximize coherence within a coaxial tunnel architecture, and realize on-chip quantum memories with single-photon Ramsey times of 2.0 - 2.7 ms, limited by their energy relaxation times of 1.0 - 1.4 ms. These results demonstrate an advancement towards a more modular and compact coaxial circuit architecture for bosonic qubits with reproducibly high coherence.

Optimizing code allocation for hybrid on-chip memory in IoT systems

With the increasing application of IoT devices, the memory subsystem, as the performance and energy bottleneck of IoT systems, has received a lot of attention. One of the keys is on-chip memory which can bridge the performance gap between the CPU and main memory. While many off-the-shelf embedded processors utilize the hybrid on-chip memory architecture containing scratchpad memories (SPMs) and caches, most existing literature ignores the collaboration between caches and SPMs. This paper proposes static SPM allocation strategies for the architecture mentioned above in IoT systems, which try to minimize the overall instruction memory subsystem latency and/or energy consumption. We capture the intra- and inter-task cache conflict misses via a fine-grained temporal cache behavior model. Based on this cache conflict information, we propose an integer linear programming (ILP) algorithm to generate an optimal static function level SPM allocation for system performance. Furthermore, to improve the scalability of the proposed allocation scheme for an enormous task set, we offer the interference factor to calculate the interference impact quantitatively. Then, based on the interference factor, we present two approximate knapsack based heuristic algorithms to provide near optimal static allocation schemes at both function- and basic block-level granularities, which favors fast design space exploration. The experiment results demonstrate that the proposed solution achieves a 30.85% improvement in memory performance, and up to 31.39% reduction in energy consumption, compared to the existing SPM allocation scheme at the function level. In addition, the proposed basic block level allocation algorithm shows better performance than our function level allocation algorithm and other basic block level allocation algorithm.

ADS-CNN: Adaptive Dataflow Scheduling for lightweight CNN accelerator on FPGAs

Lightweight convolutional neural networks (CNNs) enable lower inference latency and data traffic, facilitating deployment on resource-constrained edge devices such as field-programmable gate arrays (FPGAs). However, CNNs inference requires access to off-chip synchronous dynamic random-access memory (SDRAM), which significantly degrades inference speed and system power efficiency. In this paper, we propose an adaptive dataflow scheduling method for lightweight CNN accelerator on FPGAs named ADS-CNN. The key idea of ADS-CNN is to efficiently utilize on-chip resources and reduce the amount of SDRAM access. To achieve the reuse of logical resources, we design a time division multiplexing calculation engine to be integrated in ADS-CNN. We implement a configurable module for the convolution controller to adapt to the data reuse of different convolution layers, thus reducing the off-chip access. Furthermore, we exploit on-chip memory blocks as buffers based on the configuration of different layers in lightweight CNNs. On the resource-constrained Intel CycloneV SoC 5CSEBA6 FPGA platform, we evaluated six common lightweight CNN models to demonstrate the performance advantages of ADS-CNN. The evaluation results indicate that, compared with accelerators that use traditional tiling strategy dataflow, our ADS-CNN can achieve up to 1.29× speedup with the overall dataflow scale compression of 23.7%.

Sum and difference frequency generation in a valley-photonic-crystal-like topological system

Nonlinear sum frequency generation (SFG) and difference frequency generation (DFG) are fundamental methods to obtain new light sources for various applications. However, most of the on-chip SFG and DFG are based on conventional resonators, lacking robustness against fabrication defects. Here, we demonstrate topologically protected SFG and DFG in a second-order topological photonic system. The mechanism is based on the nonlinear interaction between three high-Q corner modes inside dual topological band gaps. The frequency matching condition for SFG and DFG is precisely satisfied by designing a valley-photonic-crystal-like topological system, which provides more freedoms to tune the corner modes. The topological SFG and DFG are achieved with high conversion efficiency, and the underlying topological physics is revealed. This work opens up avenues toward topologically protected nonlinear frequency conversion, and can find applications in the fields of on-chip single-photon detections and optical quantum memories with robustness against defects.

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training.

The rapid advancement in AI requires efficient accelerators for training on edge devices, which often face challenges related to the high hardware costs of floating-point arithmetic operations. To tackle these problems, efficient floating-point formats inspired by block floating-point (BFP), such as Microsoft Floating Point (MSFP) and FlexBlock (FB), are emerging. However, they have limited dynamic range and precision for the smaller magnitude values within a block due to the shared exponent. This limits the BFP's ability to train deep neural networks (DNNs) with diverse datasets. This paper introduces the hybrid precision (HPFP) selection algorithms, designed to systematically reduce precision and implement hybrid precision strategies, thereby balancing layer-wise arithmetic operations and data path precision to address the shortcomings of traditional floating-point formats. Reducing the data bit width with HPFP allows more read/write operations from memory per cycle, thereby decreasing off-chip data access and the size of on-chip memories. Unlike traditional reduced precision formats that use BFP for calculating partial sums and accumulating those partial sums in 32-bit Floating Point (FP32), HPFP leads to significant hardware savings by performing all multiply and accumulate operations in reduced floating-point format. For evaluation, two training accelerators for the YOLOv2-Tiny model were developed, employing distinct mixed precision strategies, and their performance was benchmarked against an accelerator utilizing a conventional brain floating point of 16 bits (Bfloat16). The HPFP selection, employing 10 bits for the data path of all layers and for the arithmetic of layers requiring low precision, along with 12 bits for layers requiring higher precision, results in a 49.4% reduction in energy consumption and a 37.5% decrease in memory access. This is achieved with only a marginal mean Average Precision (mAP) degradation of 0.8% when compared to an accelerator based on Bfloat16. This comparison demonstrates that the proposed accelerator based on HPFP can be an efficient approach to designing compact and low-power accelerators without sacrificing accuracy.

Energy efficient photonic memory based on electrically programmable embedded III-V/Si memristors: switches and filters

Over the past few years, extensive work on optical neural networks has been investigated in hopes of achieving orders of magnitude improvement in energy efficiency and compute density via all-optical matrix-vector multiplication. However, these solutions are limited by a lack of high-speed power power-efficient phase tuners, on-chip non-volatile memory, and a proper material platform that can heterogeneously integrate all the necessary components needed onto a single chip. We address these issues by demonstrating embedded multi-layer HfO2/Al2O3 memristors with III-V/Si photonics which facilitate non-volatile optical functionality for a variety of devices such as Mach-Zehnder Interferometers, and (de-)interleaver filters. The Mach-Zehnder optical memristor exhibits non-volatile optical phase shifts > π with ~33 dB signal extinction while consuming 0 electrical power consumption. We demonstrate 6 non-volatile states each capable of 4 Gbps modulation. (De-) interleaver filters were demonstrated to exhibit memristive non-volatile passband transformation with full set/reset states. Time duration tests were performed on all devices and indicated non-volatility up to 24 hours and beyond. We demonstrate non-volatile III-V/Si optical memristors with large electric-field driven phase shifts and reconfigurable filters with true 0 static power consumption. As a result, co-integrated photonic memristors offer a pathway for in-memory optical computing and large-scale non-volatile photonic circuits.

Investigation of phonon lifetimes and magnon–phonon coupling in YIG/GGG hybrid magnonic systems in the diffraction limited regime

Quantum memories facilitate the storage and retrieval of quantum information for on-chip and long-distance quantum communications. Thus, they play a critical role in quantum information processing and have diverse applications ranging from aerospace to medical imaging fields. Bulk acoustic wave (BAW) phonons are attractive candidates for quantum memories because of their long lifetimes and high operating frequencies. In this study, we establish a modeling approach to design hybrid magnonic high-overtone bulk acoustic wave resonator (HBAR) structures for high-density, long-lasting quantum memories, and efficient quantum transduction devices. We illustrate the approach by investigating a hybrid magnonic system, consisting of a gadolinium iron garnet (GGG) thick film and a patterned yttrium iron garnet (YIG) thin film. The BAW phonons are excited in GGG thick film via coupling with magnons in the YIG thin film. We present theoretical and numerical analyses of the diffraction-limited BAW phonon lifetimes, modeshapes, and magnon–phonon coupling strengths in YIG/GGG planar and confocal HBAR (CHBAR) structures. We utilize Fourier beam propagation and Hankel transform eigenvalue problem methods and compare the two methods. We discuss strategies to improve the phonon lifetimes in the diffraction-limited regime, since increased lifetimes have direct implications on the storage times of quantum states for quantum memory applications. We find that ultra-high cooperativities and phonon lifetimes on the order of ∼105 and ∼10 milliseconds, respectively, could be achieved using a CHBAR structure with 10μm YIG lateral area. Additionally, high integration density of on-chip memory or transduction centers is naturally desired for high-density memory or transduction devices. The proposed CHBAR structure will offer more than 100-fold improvement of integration density relative to a recently demonstrated YIG/GGG device. Our results will have direct applicability for devices operating in the cryogenic or milliKelvin regimes. For example, our study will inform the design of HBAR devices that could couple with superconducting qubits for promising quantum information platforms.