On-chip Interconnects Research Articles

Crosstalk Delay and Reliability Analysis of Carbon Nanotube On-Chip Interconnects: Modelling and Optimization using Metaheuristic Algorithm

In the field of VLSI technology, the miniaturization of ICs poses significant challenges to overall interconnect performance, particularly due to the rising concerns of crosstalk-induced reliability and durability issues. This work explores graphene-based randomly mixed carbon nanotube bundle (RMCB) interconnects as a viable solution for advanced reliable VLSI applications. Employing metaheuristic algorithms (Maximum Hole Degree, Particle Swarm Optimization, Stoyan and Yaskov Algorithm), this study seeks to optimize RMCB structures, maximizing carbon nanotube density within a fixed area. Notably, this study explores the effectiveness of algorithms’ performance in optimizing RMCB structures at a nano-technology node. Extensive signal integrity and reliability assessments, considering both rugged and pristine substrates, reveal that Stoyan and Yaskov (SY)-based optimization excels over PSO and MHD-based counterparts in terms of on-chip interconnect performance and reliability. The SY structure significantly dominates MHD-based (and PSO) counterparts by reducing crosstalk delay by 50% (30%), enhancing the average failure rate by 40% (37%), and improving electromigration reliability by 170% (63%).

Compact and fabrication tolerant polarization insensitive mode-order converter for MDM systems

With the increasing capacity demands of data communications, mode division multiplexing in on-chip optical interconnect systems is becoming an attractive solution. Compact, broadband, and fabrication-tolerant mode-order converters unaffected by polarizations are considered crucial for the progress of on-chip systems utilizing mode division multiplexing. A proposal for a design scheme for an on-chip mode-order converter that is insensitive to polarization is presented, utilizing a combination of 3D finite-difference time-domain (FDTD) and particle swarm optimization (PSO). The conversion of TE0/TM0-to-TE1/TM1 mode is achieved through phase matching between a subwavelength grating and an input–output tapered waveguide. Theoretical studies indicate that the TE0-to-TE1 and TM0-to-TM1 insertion losses are below 0.46 dB and 0.78 dB at a wavelength of 1550 nm. The TE0-to-TE1 and TM0-to-TM1 insertion loss is under 1.0 dB, with crosstalk below −15 dB within the 190 nm (1432∼1622 nm) and 81 nm (1515∼1596 nm) operating ranges. Experimental data indicates that the device measuring 7 × 1.58 μm2 can successfully convert mode orders regardless of polarization within an 81 nm bandwidth (1515∼1596 nm), effectively doubling the data transmission capacity of the MDM system. In addition, the devices fabricated by a standard CMOS process demonstrate the potential for mass production.

Pragmatic structure optimization: Achieving optimal crosstalk delay and gate oxide reliability of randomly mixed CNT bundle interconnects

This study explores the potential of randomly mixed carbon nanotube bundle (RMCB) as a viable on-chip interconnect. Achieving high-quality carbon nanotubes (CNTs) with uniform diameters is challenging for the current framework of enhanced fabrication techniques. The Stoyan and Yaskov technique is employed to optimize CNT arrangement within a specified rectangular area. This method accounts for statistical variation in CNT diameters, offering a more realistic and fabrication-focused approach to designing CNT bundle interconnects. Eight such practical RMCB structures (RMCB-50 to RMCB-350) are selected using this technique, each characterized by distinct CNT counts and variable diameters. Comprehensive average crosstalk-delay and reliability assessments are conducted by comparing different CNT bundle interconnects with the best-optimized RMCB (O-RMCB) interconnect, placed on various dielectric substrates such as SiO2, SiC, BN. The study unequivocally indicates that O-RMCB produces highly favorable results and stands as the most suitable future solution for VLSI circuits. Additionally, the thickness optimization of O-RMCB interconnect is explored, yielding in improvements in both performance and reliability compared to other well-known CNT bundled interconnects.

SOC chip based smart window curtain design

Relying on the rapid development of embedded systems, it becomes possible to integrate the system hardware into the same chip, and the system on chip SOC (System on Chips) is therefore birthed. This paper will be based on the SOC hardware and software co-design and verification, through the design of intelligent curtains for the specific implementation design of a kind of application in the al-in-one multi-functional machine motherboard design, the motherboard control core using SOC chip, integrated two MCU units, through the main control screen to display the control information to achieve the intelligent window switching conversion switching through the key such as manual mode, timer mode, light control mode. This design uses Keil as the software writing platform to realize the SOC master control system based on the on-chip bus interconnection. As well as this design can effectively reduce the degree of system cumbersomeness and provide smart window design ideas.

(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

The need for increased computing keeps growing at an ultra-fast speed, required to support an ever larger and wider range of applications [1]. Meanwhile, recent advances in 3D and photonic technologies are allowing new connectivity possibilities besides the typical on-chip interconnects at system-on-chip (SoC) level. This is enabling a system (r)evolution towards smart disintegration, moving away from a one-meets-all-requirements general-purpose CMOS platform, and allowing higher flexibility by separately designing and fabricating the blocks that are assembled in the final system [2]. Boosted by the novel scaling options enabled by this new approach, logic standard cell shrinkage remains at the core of the compute roadmap. Its momentum is expected to carry on by introducing new device architectures, materials, and scaling boosters such as backside (BS) power delivery (PD) [3-9]. Guided by design-technology-co-optimization (DTCO)-driven design improvements, in close interaction with the adoption of system-technology-co-optimization (STCO), the roadmap also increasingly requires EUV/high-NA EUV lithography for cost-effective, lower energy consumption, continued dimensional scaling.At transistor level, finFETs are being replaced by nanosheet (NS) FETs consisting of several vertically stacked NS per device [10,11]. Beyond that, 3D stacked CMOS, also called CFET [9,12,13], where different polarity NSFETs are folded on top of each other, appears as the ultimate scaling limit of the NS-based transistor’s family. Moreover, changes in how devices are connected are also being introduced. Moving PD to the wafer’s BS, though being a considerable disruptive technological change, is a game changer for on-chip power distribution, enabling smaller IR-drop values. This concept can be implemented in various ways, and has the potential to expand towards other functions, namely by addition of specific devices after BS processing, paving the way towards a truly functional BS [3,9,14]. Two examples of benefits brought by increased BS use are: 1) considerably more compact ESD diodes, with improved latch-up immunity, and BS contacts [9,15]; 2) lower clock latency values by moving the clock’s signal to the BS [9,16].Furthermore, as transistors are now sandwiched and accessed from levels above and below them, this also enables interesting new opportunities for device engineering. Focusing on the highly scalable BS PD scheme wherein the transistor’s source (S) (for bottom FET in case of CFET) is directly contacted from the BS (BSC-S) (Fig.1) [7,9,17,18], while the other terminals remain connected from the wafer’s frontside, several options to optimize the BSC-S’s contact resistance can be considered. These include ways to enlarge its contact surface area and the possible addition of an extra low-temperature, low-resistivity epitaxial layer [9,19,20] prior to metallization. Fig.2 also highlights the need to account for the impact on thermal performance when selecting (BSC-S)-based device configurations and materials [7,9]. Additionally, the intrinsically asymmetric S/drain (D) access with BSC-S can also be explored to enable a simpler path to build devices with differently doped S/D [9]. This can be especially interesting for high-mobility, low-bandgap FETs to mitigate IOFF concerns while still taking advantage of their high-drivability potential. CFET using, e.g., bonding technology for the bottom/top channels and their vertical isolation’s definition can also be particularly suitable for implementing distinct channel materials (like Ge-rich for bottom PMOS) as they are in separate planes.Overall, compute systems, guided by DTCO/STCO with the embrace of the use of both wafer sides, 3D stacking and sequential technologies, can potentially be assembled in ways enabling much more versatile, hybridized platforms. This can allow not only new paths for continued compute/logic scaling, but also ease the introduction of new/alternative device architectures (and materials) as they do not need to meet all the requirements of a general-purpose platform.

Broadband mode exchanger based on subwavelength Y-junctions

Abstract Multimode silicon photonics, leveraging mode-division multiplexing technologies, offers significant potential to increase capacity of large-scale multiprocessing systems for on-chip optical interconnects. These technologies have implications not only for telecom and datacom applications, but also for cutting-edge fields such as quantum and nonlinear photonics. Thus, the development of compact, low-loss and low-crosstalk multimode devices, in particular mode exchangers, is crucial for effective on-chip mode manipulation. This work introduces a novel mode exchanger that exploits the properties of subwavelength grating metamaterials and symmetric Y-junctions, achieving low losses and crosstalk over a broad bandwidth and a compact size of only 6.5 µm × 2.6 µm. The integration of SWG nanostructures in our design enables precise control of mode exchange through different propagation constants in the arms and metamaterial, and takes advantage of dispersion engineering to broaden the operating bandwidth. Experimental characterization demonstrates, to the best of our knowledge, the broadest operational bandwidth covering from 1,420 nm to 1,620 nm, with measured losses as low as 0.5 dB and extinction ratios higher than 10 dB. Enhanced performance is achieved within a 149 nm bandwidth (1,471–1,620 nm), showing measured losses below 0.4 dB and extinction ratios greater than 18 dB.

A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects

With advancements in chip technology, the number of cores in modern commercial processors continues to rise, leading to increased complexity in interconnects and on-chip networks. This complexity, however, exposes significant security vulnerabilities, primarily in the form of side-channel and covert-channel exploits. Unlike other microarchitectural side-channel attacks, those leveraging on-chip interconnects utilize unique characteristics, allowing attackers to develop novel methods that can bypass existing effective defenses. In this paper, we present a comprehensive survey of current side-channel and covert-channel attacks based on processor-on-chip interconnects. We categorize these attacks into three types: contention-based, distance-based, and layout-based, according to the specific interconnect characteristics they exploit, and discuss corresponding countermeasures for each. Finally, we provide an outlook on future development trends in processor interconnect side channels. This survey is the first to specifically focus on interconnect-based side channels in processors.

Photonic-crystal-based hybrid wavelength-mode division multiplexer for SOI platforms

This paper presents a 12-channel hybrid wavelength-mode division multiplexer (WDM-MDM) based on 2D photonic crystals. The proposed device consists of microring resonators (MRRs) and asymmetric directional couplers (ADCs) to perform three-channel wavelength division multiplexing and four-channel mode division multiplexing operations, respectively. Each MRR can work bi-directionally, providing the same wavelength channels separately in two drop ports. The bus waveguides in the cascaded ADCs are optimized to convert the fundamental modes to the corresponding higher-order modes and are connected through taper regions for the smooth transition of modes. The designed device is simulated using the finite-difference time-domain solver, achieving a maximum channel spacing and insertion loss of 5.05 nm and 0.97 dB, respectively. The device size of the proposed WDM-MDM is 74.98µm×32.82µm. The fabrication tolerance study is performed for uniform over-etch and under-etch conditions. The temperature tolerance study on the resonant wavelength is performed, and the temperature coefficient shift of <0.0254nm/K is achieved. The proposed device can potentially increase the channel capacity for on-chip high-density optical interconnects.

The impact of titanium alloying on altering nanomechanical properties and grain structures of sputter-deposited cobalt for electromigration reliability enhancement

Cobalt (Co) has recently become a highlighted on-chip interconnection material for advanced metallization scheme of microelectronic circuits. Here, electromigration behaviors of sputter-deposited Co and Co(Ti; 0.9 at%) interconnection lines embedded in Si are comparatively studied. These lines were annealed (500 °C/30 min) prior to further accelerated electromigration testing under high current densities in the range of 3 × 107–9 × 108 A cm−2. A collection of the obtained electromigration failure lifetimes, current scaling factors and activation energies confirms a noticeable enhancement in the electromigration reliability of the Co lines by the added Ti. Results by scanning transmission electron microscopy (STEM) and nanoscratch testing reveal that 3–5 nm-sized Ti crystallites are uniformly dispersed in the Co-interconnect matrix, effectively inhibiting Co grain growth, promoting the formation of nanotwinned Co and elevating film’s mechanical properties for ensuring the electromigration reliability. With deteriorated hardness and adhesion energy, reduced planar defects and many big grains all spanning transversely the entire interconnect line, Co is vulnerable to electromigration failures, also giving accelerated thermally-induced interfacial diffusion and chemical reactions with the surrounding Si, as proven by depth-profiling secondary spectrometry and STEM analysis.

Demultiplexing-free ultra-compact WDM-compatible multimode optical switch assisted by mode exchanger

Abstract Silicon-based optical switches are integral to on-chip optical interconnects, and mode-division multiplexing (MDM) technology has enabled modes to function as carriers in routing, further boosting optical switches’ link capacity. However, traditional multimode optical switches, which typically use Mach–Zehnder interferometer (MZI) structures and mode (de)multiplexers, are complex and occupy significant physical space. In this paper, we propose and experimentally demonstrate a novel demultiplexing-free dual-mode 3 × 3 thermal-optical switch based on micro-rings (MRs) and mode exchangers (MEs). All MRs are designed to handle TE1 mode, while the ME converts TE0 mode to TE1 mode, enabling separate routing of both modes. Bezier curves are employed to optimize not only the ME, but also the dual-mode 45° and 90° waveguide bends, which facilitate the flexible and compact layout design. Moreover, our structure can support multiple wavelength channels and spacings by adding pairs of MRs, exhibiting strong WDM compatibility. The switch has an ultra-compact footprint of 0.87 × 0.52 mm2. Under both “all-bar” and “all-cross” configurations, its insertion losses (ILs) remain below 8.7 dB at 1,551 nm, with optical signal-to-noise ratios (OSNRs) exceeding 13.0 dB. Also, 32 Gbps data transmission experiments validate the switch’s high-speed transmission capability.

First Principle Analysis of Borophene as an On-Chip Interconnect Material

First Principle Analysis of Borophene as an On-Chip Interconnect Material

High-speed carbon nanotube photodetector based on a planarized silicon waveguide

The integration of silicon waveguides with low-dimensional materials with excellent optoelectronic properties can enable compact and highly integrated optical devices with multiple advantages for multiple fields. A carbon nanotube (CNT) photodetector integrated on the silicon waveguide has the potential to meet on-chip high-speed optical interconnection systems, based on the outstanding properties of CNTs such as picosecond-level intrinsic photoresponse time, high charge carrier mobility, broad spectral response, high absorption coefficient, and so on. However, the thermal stability of the device may be compromised due to the local suspension in the channel for the height difference between the WG and the substrate. Here, we report a low-cost and low-optical-loss method to achieve the planarized silicon waveguide. After that, the CNT photodetectors integrated on the original and planarized waveguide with asymmetric palladium (Pd)-hafnium (Hf) metal contacts are fabricated. The influence of this planarization method on the performance of devices is analyzed via comparing the dark leakage current, the leakage current rectification ratio (CRR), the series resistances (R S ), and the photoelectric response. Finally, a CNT photodetector based on the planarized waveguide with a photocurrent (Iph) ∼510.84nA, a photoresponsivity (R I ) ∼51.04mA/W, the dark current ∼0.389µA, as well as a 3 dB bandwidth ∼34GHz at the large reverse voltage −3V is shown.

Microcracking in On-Chip Interconnect Stacks: FEM Simulation and Concept for Fatigue Test

The semiconductor industry is continuing the scaling down of both device and on-chip interconnect features, for performance and economic reasons. This trend has implications for the design of guard ring structures, i.e. metallic non-functional structures in the back-end-of-line (BEoL) stack designed to be efficient to stop microcracks. In this work, we present a sample design for an in situ experiment to study mechanical degradation and failure mechanisms of crack stop structures in the BEoL stack, to ensure the mechanical robustness of microchips for future technology nodes. Additional finite element method (FEM) simulations provide supplementary understanding of the crack kinetics. To examine the effects of mechanical loading on crack stop elements of the BEoL stack, a novel sample geometry for an in situ fatigue experiment using x-ray microscopy was developed. The x-ray microscope (ZEISS Xradia 800 Ultra) enables high-resolution imaging of the 3D-patterned sample structures and defects such as microcracks. The tailored sample geometry allows the application of a tensile load to a BEoL specimen by a lever mechanism. The feasibility of the sample design is shown by mode-I loading of a pure interconnect sample. Post-mortem analysis by scanning electron microscopy (SEM), confirming planar microcrack propagation from the notch through the dielectric layer with small deflections of the crack path near cone shaped copper vias. FEM simulations focusing on the stress-strain fields around a crack tip indicate the beginning of copper plasticity as major mechanism starting the redirection of cracks due to resulting material compression in front of the obstacle.

A comparative study of FPGA and CGRA technologies in hardware acceleration for deep learning

With the rapid growth of deep neural networks, their increasing demand for computing resources poses significant challenges to resource-constrained edge devices. Field Programmable Gate Array (FPGA) and Coarse-Grained Reconfigurable Arrays (CGRA) have emerged as promising solutions due to their parallelism and energy efficiency advantages. This paper conducts a comprehensive comparative analysis of FPGA and CGRA for accelerating deep learning workloads. It begins by introducing convolutional neural network architecture and optimization techniques. Various dataflow strategies are discussed for memory access optimization. The paper then analyzes representative cases to clarify FPGA and CGRA architectural advantages, along with optimization techniques through different dataflow strategies. The comparison reveals that FPGA offers higher throughput with fine-grained programmability for flexible bit-level operations and dataflow control. In contrast, CGRA excels in energy efficiency and area consumption with coarse-grained custom processing units and optimized on-chip interconnection networks. Quantitative comparisons are provided for throughput, energy efficiency, and area occupation. These insights can serve as a reference for selecting the appropriate architecture when designing custom hardware accelerators for deep learning workloads.

Crosstalk reduction for Arrayed waveguide gratings on Silicon-on-Insulator platform

Ultracompact silicon-based arrayed waveguide gratings (AWGs) with low loss and low crosstalk are essential for on-chip optical interconnect and miniaturized spectroscopic analysis systems. In our previous research, we demonstrated the crosstalk reduction by utilizing constant projection period for phased array waveguide on the tangent line to the grating pole to reduce the imaging error induced by phased array waveguide end point positions [1] and using deep etching waveguides at the interface of free propagation region to further decrease the footprint of phase region of an AWG to reduce fabrication imperfections induced phase error [2]. Here we first study the effect of curved waveguides in the phased array of 16 × 400 GHz AWGs on the adjacent crosstalk of output channels. According to the AWGs made in our fabrication platform and the testing results of five dies from one wafer at different locations, the AWGs with equal length of single-mode curved waveguides have an average adjacent crosstalk level of ∼ 4 dB smaller than those with equal length of narrow single-mode waveguides composed of straight and curved waveguides in their phased array. Based on the design of equal curved waveguide length in phased array, in combination with our reported approaches on crosstalk reduction, 16 × 200 GHz, 8 × 800 GHz and 8 × 1250 GHz AWGs are fabricated. For characterization, five dies including all designs from different locations of the fabricated wafer are tested. Experimental results show that among these five dies, the best adjacent crosstalk levels are less than − 21.97 dB, −25.72 dB, −24.83 dB and the worst adjacent crosstalk levels are less than − 20.51 dB, −25.03 dB, −24.34 dB for 16 × 200 GHz, 8 × 800 GHz and 8 × 1250 GHz AWGs with FPR angle of 120°, respectively, within the passband width of 25 % channel spacing. The on-chip insertion losses for all output channels of these fabricated AWGs are less than 3 dB.

Laboratory High-Contrast X-ray Microscopy of Copper Nanostructures Enabled by a Liquid-Metal-Jet X-ray Source.

High-resolution imaging of Cu/low-k on-chip interconnect stacks in advanced microelectronic products is demonstrated using full-field transmission X-ray microscopy (TXM). The comparison of two lens-based laboratory X-ray microscopes that are operated at two different photon energies, 8.0 keV and 9.2 keV, shows a contrast enhancement for imaging of copper nanostructures embedded in insulating organosilicate glass of a factor of 5 if 9.2 keV photons are used. Photons with this energy (Ga-Kα radiation) are generated from a Ga-containing target of a laboratory X-ray source applying the liquid-metal-jet technology. The 5 times higher contrast compared to the use of Cu-Kα radiation (8.0 keV photon energy) from a rotating anode X-ray source is caused by the fact that the energy of the Ga-Kα emission line is slightly higher than that of the Cu-K absorption edge (9.0 keV photon energy). The use of Ga-Kα radiation is of particular advantage for imaging of copper interconnects with dimensions from several 100 nm down to several 10 nm in a Cu/SiO2 or Cu/low-k backend-of-line stack. Physical failure analysis and reliability engineering in the semiconductor industry will benefit from high-contrast X-ray images of sub-μm copper structures in microchips.

Measuring residual stresses in individual on-chip interconnects using synchrotron nanodiffraction

As the dimensions of interconnects in integrated circuits continue to shrink, an urgent need arises to understand the physical mechanism associated with electromigration. Using x-ray nanodiffraction, we analyzed the stresses in Blech-structured pure Cu lines subjected to different electromigration conditions. The results suggest that the measured residual stresses in the early stages of electromigration are related to relaxation of stresses caused by thermal expansion mismatch, while a developing current-induced stress leads to reductions in the residual stress after longer test times. These findings not only validate the feasibility of measuring stress in copper lines using nanodiffraction but also highlight the need for a further understanding, particularly through in situ electromigration experiments with x-ray nanodiffraction analysis.

Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey

The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today’s SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. On-chip communication sub-system is shared across all the IPs and continuously used throughout the lifetime of the SoC. Therefore, the security of the on-chip communication is crucial, because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks, and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.

Anti-friction gold-based stretchable electronics enabled by interfacial diffusion-induced cohesion

Stretchable electronics that prevalently adopt chemically inert metals as sensing layers and interconnect wires have enabled high-fidelity signal acquisition for on-skin applications. However, the weak interfacial interaction between inert metals and elastomers limit the tolerance of the device to external friction interferences. Here, we report an interfacial diffusion-induced cohesion strategy that utilizes hydrophilic polyurethane to wet gold (Au) grains and render them wrapped by strong hydrogen bonding, resulting in a high interfacial binding strength of 1017.6 N/m. By further constructing a nanoscale rough configuration of the polyurethane (RPU), the binding strength of Au-RPU device increases to 1243.4 N/m, which is 100 and 4 times higher than that of conventional polydimethylsiloxane and styrene-ethylene-butylene-styrene-based devices, respectively. The stretchable Au-RPU device can remain good electrical conductivity after 1022 frictions at 130 kPa pressure, and reliably record high-fidelity electrophysiological signals. Furthermore, an anti-friction pressure sensor array is constructed based on Au-RPU interconnect wires, demonstrating a superior mechanical durability for concentrated large pressure acquisition. This chemical modification-free approach of interfacial strengthening for chemically inert metal-based stretchable electronics is promising for three-dimensional integration and on-chip interconnection.

Ultra-compact acousto-optic modulation using on-chip integrated Bragg gratings on lithium niobate-chalcogenide hybrid platform.

An ultra-compact and efficient acousto-optic modulator based on a thin-film lithium niobate-chalcogenide (ChG) hybrid platform was designed and realized. In this approach, π phase-shift Bragg grating has an ultra-short effective interaction length of only ∼ 300 µm and a compact footprint of 200 × 300 µm2. The strong microwave-acoustic coupling and superior photo-elastic property of the ChG allow us to achieve a half-wave voltage of Vπ = 1.08 V (4.07 V) for the π phase-shift Bragg grating (waveguide Bragg grating), corresponding to VπL = 0.03 V·cm (0.09 V·cm). This acousto-optic modulator exhibits a compact size, and low power consumption, and can be used for on-chip optical interconnects and microwave photonics.